On Mon, Jul 8, 2024 at 11:21 PM LIU Zhiwei <zhiwei_...@linux.alibaba.com> wrote:
>
> From: TANG Tiancheng <tangtiancheng....@alibaba-inc.com>
>
> Ensure mcause high bit is correctly set by using 32-bit width for RV32
> mode and 64-bit width for RV64 mode.
>
> Signed-off-by: TANG Tiancheng <tangtiancheng....@alibaba-inc.com>
> Reviewed-by: Liu Zhiwei <zhiwei_...@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu_helper.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 4f0ab90ac7..3eedb26cd9 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -1673,6 +1673,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> target_ulong tinst = 0;
> target_ulong htval = 0;
> target_ulong mtval2 = 0;
> + int sxlen = 0;
> + int mxlen = 0;
>
> if (!async) {
> /* set tval to badaddr for traps with address information */
> @@ -1799,7 +1801,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> s = set_field(s, MSTATUS_SPP, env->priv);
> s = set_field(s, MSTATUS_SIE, 0);
> env->mstatus = s;
> - env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS -
> 1));
> + sxlen = 16 << riscv_cpu_sxl(env);
> + env->scause = cause | ((target_ulong)async << (sxlen - 1));
> env->sepc = env->pc;
> env->stval = tval;
> env->htval = htval;
> @@ -1830,7 +1833,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> s = set_field(s, MSTATUS_MPP, env->priv);
> s = set_field(s, MSTATUS_MIE, 0);
> env->mstatus = s;
> - env->mcause = cause | ~(((target_ulong)-1) >> async);
> + mxlen = 16 << riscv_cpu_mxl(env);
> + env->mcause = cause | ((target_ulong)async << (mxlen - 1));
> env->mepc = env->pc;
> env->mtval = tval;
> env->mtval2 = mtval2;
> --
> 2.43.0
>
>
