On Wed, Jun 12, 2024 at 6:15 PM Jim Shu <jim....@sifive.com> wrote:
>
> RISC-V WorldGuard will add 5-bit world_id (WID) to the each memory
> transaction on the bus. The wgChecker in front of RAM or peripherals
> MMIO could do the access control based on the WID. It is similar to ARM
> TrustZone NS bit, but the WID is 5-bit.
>
> The common implementation of WID is AXI4 AxUSER signal.
>
> Signed-off-by: Jim Shu <jim....@sifive.com>
> ---
> include/exec/memattrs.h | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
> index 14cdd8d582..d00f3c5500 100644
> --- a/include/exec/memattrs.h
> +++ b/include/exec/memattrs.h
> @@ -52,6 +52,11 @@ typedef struct MemTxAttrs {
> unsigned int memory:1;
> /* Requester ID (for MSI for example) */
> unsigned int requester_id:16;
> +
> + /*
> + * RISC-V WorldGuard: the 5-bit WID of memory access.
> + */
> + uint8_t world_id;
Everything else is using `unsigned int` so I think we should as well
Alistair
> } MemTxAttrs;
>
> /* Bus masters which don't specify any attributes will get this,
> --
> 2.17.1
>
>
