This is a ping to the patch below. https://lore.kernel.org/qemu-devel/ty0pr0101mb42850337f8917d1f514107fba4...@ty0pr0101mb4285.apcprd01.prod.exchangelabs.com/
________________________________ 差出人: 伊藤 太清 <taisei1...@outlook.jp> 送信日時: 2024年7月5日 12:33 宛先: qemu-devel@nongnu.org <qemu-devel@nongnu.org> CC: pbonz...@redhat.com <pbonz...@redhat.com>; m...@redhat.com <m...@redhat.com> 件名: [PING][PATCH] hw/intc/ioapic: Delete a wrong IRQ redirection on I/O APIC This is a ping to the patch below. https://lore.kernel.org/qemu-devel/ty0pr0101mb42850337f8917d1f514107fba4...@ty0pr0101mb4285.apcprd01.prod.exchangelabs.com/ ________________________________ 差出人: TaiseiIto <taisei1...@outlook.jp> 送信日時: 2024年6月25日 21:03 宛先: qemu-devel@nongnu.org <qemu-devel@nongnu.org> CC: pbonz...@redhat.com <pbonz...@redhat.com>; m...@redhat.com <m...@redhat.com>; TaiseiIto <taisei1...@outlook.jp> 件名: [PATCH] hw/intc/ioapic: Delete a wrong IRQ redirection on I/O APIC Before this commit, interruptions from i8254 which should be sent to IRQ0 were sent to IRQ2. After this commit, these are correctly sent to IRQ0. When I had an HPET timer generate interruptions once per second to test an HPET driver in my operating system on QEMU, I observed more frequent interruptions than I configured on the HPET timer. I investigated the cause and found that not only interruptions from HPET but also interruptions from i8254 were sent to IRQ2 because of a redirection from IRQ0 to IRQ2. This redirection is added in hw/apic.c at commit 16b29ae1807b024bd5052301550f5d47dae958a2 but this redirection caused wrong interruptions. So I deleted the redirection. Finally, I confirmed there is no problem on 'make check' results and that interruptions from i8254 and interruptions from HPET are correclty sent to IRQ0 and IRQ2 respectively. Signed-off-by: TaiseiIto <taisei1...@outlook.jp> --- hw/intc/ioapic.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c index 716ffc8bbb..6b630b45ca 100644 --- a/hw/intc/ioapic.c +++ b/hw/intc/ioapic.c @@ -154,15 +154,8 @@ static void ioapic_set_irq(void *opaque, int vector, int level) { IOAPICCommonState *s = opaque; - /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps - * to GSI 2. GSI maps to ioapic 1-1. This is not - * the cleanest way of doing it but it should work. */ - trace_ioapic_set_irq(vector, level); ioapic_stat_update_irq(s, vector, level); - if (vector == 0) { - vector = 2; - } if (vector < IOAPIC_NUM_PINS) { uint32_t mask = 1 << vector; uint64_t entry = s->ioredtbl[vector]; -- 2.34.1
