On Thu, Jul 18, 2024 at 06:07:37PM GMT, Alexandre Ghiti wrote: > The Svvptc extension describes a uarch that does not cache invalid TLB > entries: that's the case for qemu so there is nothing particular to > implement other than the introduction of this extension. > > Since qemu already exposes Svvptc behaviour, let's enable it by default > since it allows to drastically reduce the number of sfence.vma emitted > by S-mode. > > Signed-off-by: Alexandre Ghiti <alexgh...@rivosinc.com> > --- > Changes in v2: > - Rebase on top of master > - Enable Svvptc by default > > target/riscv/cpu.c | 2 ++ > target/riscv/cpu_cfg.h | 1 + > 2 files changed, 3 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index c53b0d5b40..19421c8a45 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -192,6 +192,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), > ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), > ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), > + ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_12_0, ext_svvptc),
Since Svvptc was just ratified then it isn't spec 1.12. We need another patch adding later versions first (there is at least one [1]). [1] https://lists.gnu.org/archive/html/qemu-riscv/2024-05/msg00045.html This version field is annoying to keep accurate... Maybe we should make it optional and only specify a version when there are wider spread changes, such as envcfg bits, which need to be present too. > ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), > ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), > ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), > @@ -1499,6 +1500,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false), > MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false), > MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false), > + MULTI_EXT_CFG_BOOL("svvptc", ext_svvptc, true), > > MULTI_EXT_CFG_BOOL("zicntr", ext_zicntr, true), > MULTI_EXT_CFG_BOOL("zihpm", ext_zihpm, true), > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index fb7eebde52..62612ae348 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -78,6 +78,7 @@ struct RISCVCPUConfig { > bool ext_svinval; > bool ext_svnapot; > bool ext_svpbmt; > + bool ext_svvptc; > bool ext_zdinx; > bool ext_zaamo; > bool ext_zacas; > -- > 2.39.2 > > Thanks, drew