>-----Original Message----- >From: CLEMENT MATHIEU--DRIF <clement.mathieu--d...@eviden.com> >Subject: Re: [PATCH v1 17/17] tests/qtest: Add intel-iommu test > > > >On 18/07/2024 10:16, Zhenzhong Duan wrote: >> Caution: External email. Do not open attachments or click links, unless this >email comes from a known sender and you know the content is safe. >> >> >> Add the framework to test the intel-iommu device. >> >> Currently only tested cap/ecap bits correctness in scalable >> modern mode. Also tested cap/ecap bits consistency before >> and after system reset. >> >> Signed-off-by: Zhenzhong Duan <zhenzhong.d...@intel.com> >> --- >> MAINTAINERS | 1 + >> include/hw/i386/intel_iommu.h | 1 + >> tests/qtest/intel-iommu-test.c | 71 >++++++++++++++++++++++++++++++++++ >> tests/qtest/meson.build | 1 + >> 4 files changed, 74 insertions(+) >> create mode 100644 tests/qtest/intel-iommu-test.c >> >> diff --git a/MAINTAINERS b/MAINTAINERS >> index 7d9811458c..ec765bf3d3 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -3662,6 +3662,7 @@ S: Supported >> F: hw/i386/intel_iommu.c >> F: hw/i386/intel_iommu_internal.h >> F: include/hw/i386/intel_iommu.h >> +F: tests/qtest/intel-iommu-test.c >> >> AMD-Vi Emulation >> S: Orphan >> diff --git a/include/hw/i386/intel_iommu.h >b/include/hw/i386/intel_iommu.h >> index 650641544c..b1848dbec6 100644 >> --- a/include/hw/i386/intel_iommu.h >> +++ b/include/hw/i386/intel_iommu.h >> @@ -47,6 +47,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(IntelIOMMUState, >INTEL_IOMMU_DEVICE) >> #define VTD_HOST_AW_48BIT 48 >> #define VTD_HOST_AW_AUTO 0xff >> #define VTD_HAW_MASK(aw) ((1ULL << (aw)) - 1) >> +#define VTD_MGAW_FROM_CAP(cap) ((cap >> 16) & 0x3fULL) >> >> #define DMAR_REPORT_F_INTR (1) >> >> diff --git a/tests/qtest/intel-iommu-test.c b/tests/qtest/intel-iommu-test.c >> new file mode 100644 >> index 0000000000..8e07034f6f >> --- /dev/null >> +++ b/tests/qtest/intel-iommu-test.c >> @@ -0,0 +1,71 @@ >> +/* >> + * QTest testcase for intel-iommu >> + * >> + * Copyright (c) 2024 Intel, Inc. >> + * >> + * Author: Zhenzhong Duan <zhenzhong.d...@intel.com> >> + * >> + * This work is licensed under the terms of the GNU GPL, version 2 or >later. >> + * See the COPYING file in the top-level directory. >> + */ >> + >> +#include "qemu/osdep.h" >> +#include "libqtest.h" >> +#include "hw/i386/intel_iommu_internal.h" >> + >> +#define CAP_MODERN_FIXED1 (VTD_CAP_FRO | VTD_CAP_NFR | >VTD_CAP_ND | \ >> + VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS) >> +#define ECAP_MODERN_FIXED1 (VTD_ECAP_QI | VTD_ECAP_IRO | >VTD_ECAP_MHMV | \ >> + VTD_ECAP_SMTS | VTD_ECAP_FLTS) >> + >> +static inline uint32_t vtd_reg_readl(QTestState *s, uint64_t offset) >> +{ >> + return qtest_readl(s, Q35_HOST_BRIDGE_IOMMU_ADDR + offset); >> +} >> + >> +static inline uint64_t vtd_reg_readq(QTestState *s, uint64_t offset) >> +{ >> + return qtest_readq(s, Q35_HOST_BRIDGE_IOMMU_ADDR + offset); >> +} >> + >> +static void test_intel_iommu_modern(void) >> +{ >> + uint8_t init_csr[DMAR_REG_SIZE]; /* register values */ >> + uint8_t post_reset_csr[DMAR_REG_SIZE]; /* register values */ >> + uint64_t cap, ecap, tmp; >> + QTestState *s; >> + >> + s = qtest_init("-M q35 -device intel-iommu,x-scalable-mode=modern"); >> + >> + cap = vtd_reg_readq(s, DMAR_CAP_REG); >> + g_assert((cap & CAP_MODERN_FIXED1) == CAP_MODERN_FIXED1); >> + >> + tmp = cap & VTD_CAP_SAGAW_MASK; >> + g_assert(tmp == (VTD_CAP_SAGAW_39bit | VTD_CAP_SAGAW_48bit)); >> + >> + tmp = VTD_MGAW_FROM_CAP(cap); >> + g_assert(tmp == VTD_HOST_AW_48BIT - 1); >> + >> + ecap = vtd_reg_readq(s, DMAR_ECAP_REG); >> + g_assert((ecap & ECAP_MODERN_FIXED1) == ECAP_MODERN_FIXED1); >> + g_assert(ecap & VTD_ECAP_IR); >Can we add VTD_ECAP_IR to ECAP_MODERN_FIXED1?
Will do. Thanks Zhenzhong >> + >> + qtest_memread(s, Q35_HOST_BRIDGE_IOMMU_ADDR, init_csr, >DMAR_REG_SIZE); >> + >> + qobject_unref(qtest_qmp(s, "{ 'execute': 'system_reset' }")); >> + qtest_qmp_eventwait(s, "RESET"); >> + >> + qtest_memread(s, Q35_HOST_BRIDGE_IOMMU_ADDR, post_reset_csr, >DMAR_REG_SIZE); >> + /* Ensure registers are consistent after hard reset */ >> + g_assert(!memcmp(init_csr, post_reset_csr, DMAR_REG_SIZE)); >> + >> + qtest_quit(s); >> +} >> + >> +int main(int argc, char **argv) >> +{ >> + g_test_init(&argc, &argv, NULL); >> + qtest_add_func("/q35/intel-iommu/modern", >test_intel_iommu_modern); >> + >> + return g_test_run(); >> +} >> diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build >> index 6508bfb1a2..20d05d471b 100644 >> --- a/tests/qtest/meson.build >> +++ b/tests/qtest/meson.build >> @@ -79,6 +79,7 @@ qtests_i386 = \ >> (config_all_devices.has_key('CONFIG_SB16') ? ['fuzz-sb16-test'] : []) + >\ >> (config_all_devices.has_key('CONFIG_SDHCI_PCI') ? ['fuzz-sdcard-test'] : >[]) + \ >> (config_all_devices.has_key('CONFIG_ESP_PCI') ? ['am53c974-test'] : []) >+ \ >> + (config_all_devices.has_key('CONFIG_VTD') ? ['intel-iommu-test'] : []) + >\ >> (host_os != 'windows' and >> \ >> config_all_devices.has_key('CONFIG_ACPI_ERST') ? ['erst-test'] : []) + >\ >> (config_all_devices.has_key('CONFIG_PCIE_PORT') and >\ >> -- >> 2.34.1 >> > >Reviewed-by: Clément Mathieu--Drif<clement.mathieu--d...@eviden.com>