On 8/2/24 17:24, LIU Zhiwei wrote:
According to the risc-v specification:
"FLD and FSD are only guaranteed to execute atomically if the effective
address is naturally aligned and XLEN≥64."
We currently implement fld as MO_ATOM_IFALIGN when XLEN < 64, which does
not violate the rules. But it will hide some problems. So relax it to
MO_ATOM_NONE.
Signed-off-by: LIU Zhiwei<zhiwei_...@linux.alibaba.com>
---
target/riscv/insn_trans/trans_rvd.c.inc | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
r~
