Add test to exercise clocks set and clear, system PLL initialization,
audio PLL initialization, systick and ostimer clock source selection.
Signed-off-by: Octavian Purdila <ta...@google.com>
---
tests/unit/meson.build | 7 +
tests/unit/test-rt500-clkctl.c | 270 +++++++++++++++++++++++++++++++++
2 files changed, 277 insertions(+)
create mode 100644 tests/unit/test-rt500-clkctl.c
diff --git a/tests/unit/meson.build b/tests/unit/meson.build
index 7a28e7b521..be3062acbf 100644
--- a/tests/unit/meson.build
+++ b/tests/unit/meson.build
@@ -188,6 +188,13 @@ if have_system
meson.project_source_root() / 'hw/ssi/ssi.c',
'spi_tester.c',
],
+ 'test-rt500-clkctl': [
+ hwcore,
+ meson.project_source_root() / 'hw/core/gpio.c',
+ meson.project_source_root() / 'hw/misc/rt500_clkctl0.c',
+ meson.project_source_root() / 'hw/misc/rt500_clkctl1.c',
+ meson.project_source_root() / 'tests/unit/sysbus-mock.c',
+ ],
}
if config_host_data.get('CONFIG_INOTIFY1')
tests += {'test-util-filemonitor': []}
diff --git a/tests/unit/test-rt500-clkctl.c b/tests/unit/test-rt500-clkctl.c
new file mode 100644
index 0000000000..9312091c46
--- /dev/null
+++ b/tests/unit/test-rt500-clkctl.c
@@ -0,0 +1,270 @@
+/*
+ * Copyright (c) 2024 Google LLC
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/main-loop.h"
+#include "exec/memory.h"
+#include "hw/clock.h"
+#include "hw/irq.h"
+#include "hw/qdev-clock.h"
+#include "hw/qdev-properties.h"
+
+#include "hw/misc/rt500_clkctl0.h"
+#include "hw/misc/rt500_clkctl1.h"
+#include "hw/misc/rt500_clk_freqs.h"
+#include "sysbus-mock.h"
+#include "reg-utils.h"
+
+typedef struct {
+ DeviceState *clk0;
+ DeviceState *clk1;
+ Clock *sysclk;
+ Clock *systick_clk;
+ Clock *ostimer_clk;
+} TestFixture;
+
+#define SYSCLK_HZ 100000000
+
+#define RT500_CLKCTL0_BASE 0x40001000UL
+#define RT500_CLKCTL1_BASE 0x40021000UL
+
+/*
+ * Test fixture initialization.
+ */
+static void set_up(TestFixture *f, gconstpointer data)
+{
+ f->clk0 = qdev_new(TYPE_RT500_CLKCTL0);
+ g_assert(f->clk0);
+
+ f->clk1 = qdev_new(TYPE_RT500_CLKCTL1);
+ g_assert(f->clk1);
+
+ f->sysclk = clock_new(OBJECT(&f->clk0->parent_obj), "SYSCLK");
+ clock_set_hz(f->sysclk, SYSCLK_HZ);
+
+ qdev_connect_clock_in(f->clk0, "sysclk", f->sysclk);
+ f->systick_clk = RT500_CLKCTL0(f->clk0)->systick_clk;
+
+ qdev_connect_clock_in(f->clk1, "sysclk", f->sysclk);
+ f->ostimer_clk = RT500_CLKCTL1(f->clk1)->ostimer_clk;
+
+ qdev_realize_and_unref(f->clk0, NULL, NULL);
+ sysbus_mmio_map(SYS_BUS_DEVICE(f->clk0), 0, RT500_CLKCTL0_BASE);
+
+ qdev_realize_and_unref(f->clk1, NULL, NULL);
+ sysbus_mmio_map(SYS_BUS_DEVICE(f->clk1), 0, RT500_CLKCTL1_BASE);
+
+ device_cold_reset(f->clk0);
+ device_cold_reset(f->clk1);
+}
+
+static void tear_down(TestFixture *f, gconstpointer user_data)
+{
+ qdev_unrealize(f->clk0);
+ qdev_unrealize(f->clk1);
+ g_free(f->clk0);
+ g_free(f->clk1);
+}
+
+#undef CLKCTL0
+#undef CLKCTL1
+
+static void pscctl_test(TestFixture *f, gconstpointer user_data)
+{
+ /* rom controller clock should be enabled at reset */
+ g_assert(REG32_READ_FIELD(f->clk0, RT500_CLKCTL0, PSCCTL0, ROM_CTRLR_CLK)
+ == 1);
+
+ /* DSP clk is disabled at reset */
+ g_assert(REG32_READ_FIELD(f->clk0, RT500_CLKCTL0, PSCCTL0, DSP_CLK) == 0);
+
+ /* check PSCTL_SET functionality */
+ REG32_WRITE(f->clk0, RT500_CLKCTL0, PSCCTL0_SET,
+ RT500_CLKCTL0_PSCCTL0_DSP_CLK_Msk);
+ g_assert(REG32_READ_FIELD(f->clk0, RT500_CLKCTL0, PSCCTL0, DSP_CLK) == 1);
+
+ /* check PSCTL_CLR functionality */
+ REG32_WRITE(f->clk0, RT500_CLKCTL0, PSCCTL0_CLR,
+ RT500_CLKCTL0_PSCCTL0_DSP_CLK_Msk);
+ g_assert(REG32_READ_FIELD(f->clk0, RT500_CLKCTL0, PSCCTL0, DSP_CLK) == 0);
+
+ /* FLEXIO clk is disabled at reset */
+ g_assert(REG32_READ_FIELD(f->clk1, RT500_CLKCTL1, PSCCTL0, FlexIO) == 0);
+
+ /* check PSCTL_SET functionality */
+ REG32_WRITE(f->clk1, RT500_CLKCTL1, PSCCTL0_SET,
+ RT500_CLKCTL1_PSCCTL0_FlexIO_Msk);
+ g_assert(REG32_READ_FIELD(f->clk1, RT500_CLKCTL1, PSCCTL0, FlexIO) == 1);
+
+ /* check PSCTL_CLR functionality */
+ REG32_WRITE(f->clk1, RT500_CLKCTL1, PSCCTL0_CLR,
+ RT500_CLKCTL1_PSCCTL0_FlexIO_Msk);
+ g_assert(REG32_READ_FIELD(f->clk1, RT500_CLKCTL1, PSCCTL0, FlexIO) == 0);
+}
+
+static void audiopll0pfd_test(TestFixture *f, gconstpointer user_data)
+{
+ /* audio plls are gated at boot */
+ g_assert(REG32_READ_FIELD(f->clk1, RT500_CLKCTL1, AUDIOPLL0PFD,
+ PFD3_CLKGATE) == 1);
+ g_assert(REG32_READ_FIELD(f->clk1, RT500_CLKCTL1, AUDIOPLL0PFD,
+ PFD2_CLKGATE) == 1);
+ g_assert(REG32_READ_FIELD(f->clk1, RT500_CLKCTL1, AUDIOPLL0PFD,
+ PFD1_CLKGATE) == 1);
+ g_assert(REG32_READ_FIELD(f->clk1, RT500_CLKCTL1, AUDIOPLL0PFD,
+ PFD0_CLKGATE) == 1);
+
+ /* ,,, and clocks are not ready */
+ g_assert(REG32_READ_FIELD(f->clk1, RT500_CLKCTL1, AUDIOPLL0PFD,
PFD3_CLKRDY)
+ == 0);
+ g_assert(REG32_READ_FIELD(f->clk1, RT500_CLKCTL1, AUDIOPLL0PFD,
PFD2_CLKRDY)
+ == 0);
+ g_assert(REG32_READ_FIELD(f->clk1, RT500_CLKCTL1, AUDIOPLL0PFD,
PFD1_CLKRDY)
+ == 0);
+ g_assert(REG32_READ_FIELD(f->clk1, RT500_CLKCTL1, AUDIOPLL0PFD,
PFD0_CLKRDY)
+ == 0);
+
+ /* ungate all plls and check that clocks are ready */
+ REG32_WRITE_FIELD(f->clk1, RT500_CLKCTL1, AUDIOPLL0PFD, PFD3_CLKGATE, 0);
+ REG32_WRITE_FIELD(f->clk1, RT500_CLKCTL1, AUDIOPLL0PFD, PFD2_CLKGATE, 0);
+ REG32_WRITE_FIELD(f->clk1, RT500_CLKCTL1, AUDIOPLL0PFD, PFD1_CLKGATE, 0);
+ REG32_WRITE_FIELD(f->clk1, RT500_CLKCTL1, AUDIOPLL0PFD, PFD0_CLKGATE, 0);
+
+ g_assert(REG32_READ_FIELD(f->clk1, RT500_CLKCTL1, AUDIOPLL0PFD,
PFD3_CLKRDY)
+ == 1);
+ g_assert(REG32_READ_FIELD(f->clk1, RT500_CLKCTL1, AUDIOPLL0PFD,
PFD2_CLKRDY)
+ == 1);
+ g_assert(REG32_READ_FIELD(f->clk1, RT500_CLKCTL1, AUDIOPLL0PFD,
PFD1_CLKRDY)
+ == 1);
+ g_assert(REG32_READ_FIELD(f->clk1, RT500_CLKCTL1, AUDIOPLL0PFD,
PFD0_CLKRDY)
+ == 1);
+}
+
+static void syspll0pfd_test(TestFixture *f, gconstpointer user_data)
+{
+ /* system plls are gated at boot */
+ g_assert(REG32_READ_FIELD(f->clk0, RT500_CLKCTL0, SYSPLL0PFD, PFD3_CLKGATE)
+ == 1);
+ g_assert(REG32_READ_FIELD(f->clk0, RT500_CLKCTL0, SYSPLL0PFD, PFD2_CLKGATE)
+ == 1);
+ g_assert(REG32_READ_FIELD(f->clk0, RT500_CLKCTL0, SYSPLL0PFD, PFD1_CLKGATE)
+ == 1);
+ g_assert(REG32_READ_FIELD(f->clk0, RT500_CLKCTL0, SYSPLL0PFD, PFD0_CLKGATE)
+ == 1);
+
+ /* ,,, and clocks are not ready */
+ g_assert(REG32_READ_FIELD(f->clk0, RT500_CLKCTL0, SYSPLL0PFD, PFD3_CLKRDY)
+ == 0);
+ g_assert(REG32_READ_FIELD(f->clk0, RT500_CLKCTL0, SYSPLL0PFD, PFD2_CLKRDY)
+ == 0);
+ g_assert(REG32_READ_FIELD(f->clk0, RT500_CLKCTL0, SYSPLL0PFD, PFD1_CLKRDY)
+ == 0);
+ g_assert(REG32_READ_FIELD(f->clk0, RT500_CLKCTL0, SYSPLL0PFD, PFD0_CLKRDY)
+ == 0);
+
+ /* ungate all plls and check that clocks are ready */
+ REG32_WRITE_FIELD(f->clk0, RT500_CLKCTL0, SYSPLL0PFD, PFD3_CLKGATE, 0);
+ REG32_WRITE_FIELD(f->clk0, RT500_CLKCTL0, SYSPLL0PFD, PFD2_CLKGATE, 0);
+ REG32_WRITE_FIELD(f->clk0, RT500_CLKCTL0, SYSPLL0PFD, PFD1_CLKGATE, 0);
+ REG32_WRITE_FIELD(f->clk0, RT500_CLKCTL0, SYSPLL0PFD, PFD0_CLKGATE, 0);
+
+ g_assert(REG32_READ_FIELD(f->clk0, RT500_CLKCTL0, SYSPLL0PFD, PFD3_CLKRDY)
+ == 1);
+ g_assert(REG32_READ_FIELD(f->clk0, RT500_CLKCTL0, SYSPLL0PFD, PFD2_CLKRDY)
+ == 1);
+ g_assert(REG32_READ_FIELD(f->clk0, RT500_CLKCTL0, SYSPLL0PFD, PFD1_CLKRDY)
+ == 1);
+ g_assert(REG32_READ_FIELD(f->clk0, RT500_CLKCTL0, SYSPLL0PFD, PFD0_CLKRDY)
+ == 1);
+}
+
+static void systick_clk_test(TestFixture *f, gconstpointer user_data)
+{
+ /* systick is not running at reset */
+ g_assert(clock_get_hz(f->systick_clk) == 0);
+
+ /* select divout no divisor */
+ REG32_WRITE_FIELD(f->clk0, RT500_CLKCTL0, SYSTICKFCLKSEL, SEL,
+ SYSTICKFCLKSEL_DIVOUT);
+ g_assert(clock_get_hz(f->systick_clk) == SYSCLK_HZ);
+
+ /* change divisor to 2 */
+ REG32_WRITE_FIELD(f->clk0, RT500_CLKCTL0, SYSTICKFCLKDIV, DIV, 1);
+ g_assert(clock_get_hz(f->systick_clk) == SYSCLK_HZ / 2);
+
+ /* select lpsoc */
+ REG32_WRITE_FIELD(f->clk0, RT500_CLKCTL0, SYSTICKFCLKSEL, SEL,
+ SYSTICKFCLKSEL_LPOSC);
+ g_assert(clock_get_hz(f->systick_clk) == LPOSC_CLK_HZ);
+
+ /* select lpsoc */
+ REG32_WRITE_FIELD(f->clk0, RT500_CLKCTL0, SYSTICKFCLKSEL, SEL,
+ SYSTICKFCLKSEL_32KHZRTC);
+ g_assert(clock_get_hz(f->systick_clk) == RTC32KHZ_CLK_HZ);
+
+ /* disable clock */
+ REG32_WRITE_FIELD(f->clk0, RT500_CLKCTL0, SYSTICKFCLKSEL, SEL,
+ SYSTICKFCLKSEL_NONE);
+ g_assert(clock_get_hz(f->systick_clk) == 0);
+}
+
+static void ostimer_clk_test(TestFixture *f, gconstpointer user_data)
+{
+ /* systick is not running at reset */
+ g_assert(clock_get_hz(f->ostimer_clk) == 0);
+
+ /* select lpsoc */
+ REG32_WRITE_FIELD(f->clk1, RT500_CLKCTL1, OSEVENTTFCLKSEL, SEL,
+ OSEVENTTFCLKSEL_LPOSC);
+ g_assert(clock_get_hz(f->ostimer_clk) == LPOSC_CLK_HZ);
+
+
+ /* select 32khz RTC */
+ REG32_WRITE_FIELD(f->clk1, RT500_CLKCTL1, OSEVENTTFCLKSEL, SEL,
+ OSEVENTTFCLKSEL_32KHZRTC);
+ g_assert(clock_get_hz(f->ostimer_clk) == RTC32KHZ_CLK_HZ);
+
+ /* select hclk */
+ REG32_WRITE_FIELD(f->clk1, RT500_CLKCTL1, OSEVENTTFCLKSEL, SEL,
+ OSEVENTTFCLKSEL_HCLK);
+ g_assert(clock_get_hz(f->ostimer_clk) == SYSCLK_HZ);
+
+ /* disable clock */
+ REG32_WRITE_FIELD(f->clk1, RT500_CLKCTL1, OSEVENTTFCLKSEL, SEL,
+ OSEVENTTFCLKSEL_NONE);
+ g_assert(clock_get_hz(f->ostimer_clk) == 0);
+}
+
+int main(int argc, char **argv)
+{
+ g_test_init(&argc, &argv, NULL);
+
+ /* Initialize object types. */
+ sysbus_mock_init();
+ module_call_init(MODULE_INIT_QOM);
+
+ g_test_add("/rt500-clkctl/pscctl-test", TestFixture, NULL,
+ set_up, pscctl_test, tear_down);
+
+ g_test_add("/rt500-clkctl/syspll0pfd-test", TestFixture, NULL,
+ set_up, syspll0pfd_test, tear_down);
+
+ g_test_add("/rt500-clkctl/audiopll0pfd-test", TestFixture, NULL,
+ set_up, audiopll0pfd_test, tear_down);
+
+ g_test_add("/rt500-clkctl/systick-test", TestFixture, NULL,
+ set_up, systick_clk_test, tear_down);
+
+ g_test_add("/rt500-clkctl/ostimer-clk-test", TestFixture, NULL,
+ set_up, ostimer_clk_test, tear_down);
+
+ return g_test_run();
+}
--
2.46.0.rc2.264.g509ed76dc8-goog
