On Wed, Jul 24, 2024 at 9:33 AM Atish Patra <ati...@rivosinc.com> wrote:
>
> From: Kaiwen Xue <kaiw...@rivosinc.com>
>
> This adds definitions for counter delegation, including the new
> scountinhibit register and the mstateen.CD bit.
>
> Signed-off-by: Atish Patra <ati...@rivosinc.com>
> Signed-off-by: Kaiwen Xue <kaiw...@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 1 +
> target/riscv/cpu_bits.h | 8 +++++++-
> target/riscv/machine.c | 1 +
> 3 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 1619c3acb666..af25550a4a54 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -368,6 +368,7 @@ struct CPUArchState {
> uint32_t scounteren;
> uint32_t mcounteren;
>
> + uint32_t scountinhibit;
> uint32_t mcountinhibit;
>
> /* PMU cycle & instret privilege mode filtering */
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 2a8b53a6622e..d20468412dca 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -207,6 +207,9 @@
> #define CSR_SSTATEEN2 0x10E
> #define CSR_SSTATEEN3 0x10F
>
> +/* Supervisor Counter Delegation */
> +#define CSR_SCOUNTINHIBIT 0x120
> +
> /* Supervisor Trap Handling */
> #define CSR_SSCRATCH 0x140
> #define CSR_SEPC 0x141
> @@ -778,6 +781,7 @@ typedef enum RISCVException {
> #define MENVCFG_CBIE (3UL << 4)
> #define MENVCFG_CBCFE BIT(6)
> #define MENVCFG_CBZE BIT(7)
> +#define MENVCFG_CDE (1ULL << 60)
> #define MENVCFG_ADUE (1ULL << 61)
> #define MENVCFG_PBMTE (1ULL << 62)
> #define MENVCFG_STCE (1ULL << 63)
> @@ -869,7 +873,9 @@ typedef enum RISCVException {
> #define ISELECT_IMSIC_LAST ISELECT_IMSIC_EIE63
> #define ISELECT_MASK_AIA 0x1ff
>
> -/* MISELECT, SISELECT, and VSISELECT bits (AIA) */
> +/* [M|S|VS]SELCT value for Indirect CSR Access Extension */
> +#define ISELECT_CD_FIRST 0x40
> +#define ISELECT_CD_LAST 0x5f
> #define ISELECT_MASK_SXCSRIND 0xfff
>
> /* Dummy [M|S|VS]ISELECT value for emulating [M|S|VS]TOPEI CSRs */
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 492c2c6d9d79..1a2a68407852 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -398,6 +398,7 @@ const VMStateDescription vmstate_riscv_cpu = {
> VMSTATE_UINTTL(env.siselect, RISCVCPU),
> VMSTATE_UINT32(env.scounteren, RISCVCPU),
> VMSTATE_UINT32(env.mcounteren, RISCVCPU),
> + VMSTATE_UINT32(env.scountinhibit, RISCVCPU),
> VMSTATE_UINT32(env.mcountinhibit, RISCVCPU),
> VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0,
> vmstate_pmu_ctr_state, PMUCTRState),
>
> --
> 2.34.1
>
>
