ping
Jason Chien <jason.ch...@sifive.com> 於 2024年7月23日 週二 上午1:50寫道：
> RVV spec allows implementations to set vl with values within
> [ceil(AVL/2),VLMAX] when VLMAX < AVL < 2*VLMAX. This commit adds a
> property "rvv_vl_half_avl" to enable setting vl = ceil(AVL/2). This
> behavior helps identify compiler issues and bugs.
>
> Signed-off-by: Jason Chien <jason.ch...@sifive.com>
> ---
> target/riscv/cpu.c | 1 +
> target/riscv/cpu_cfg.h | 1 +
> target/riscv/vector_helper.c | 2 ++
> 3 files changed, 4 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index a90808a3ba..8f21171ffa 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2687,6 +2687,7 @@ static Property riscv_cpu_properties[] = {
>
> DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false),
> DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false),
> + DEFINE_PROP_BOOL("rvv_vl_half_avl", RISCVCPU, cfg.rvv_vl_half_avl,
> false),
>
> /*
> * write_misa() is marked as experimental for now so mark
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index 8b272fb826..96fe26d4ea 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -127,6 +127,7 @@ struct RISCVCPUConfig {
> bool ext_smepmp;
> bool rvv_ta_all_1s;
> bool rvv_ma_all_1s;
> + bool rvv_vl_half_avl;
>
> uint32_t mvendorid;
> uint64_t marchid;
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 1b4d5a8e37..825312552b 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -75,6 +75,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env,
> target_ulong s1,
> vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul);
> if (s1 <= vlmax) {
> vl = s1;
> + } else if (s1 < 2 * vlmax && cpu->cfg.rvv_vl_half_avl) {
> + vl = (s1 + 1) >> 1;
> } else {
> vl = vlmax;
> }
> --
> 2.43.2
>
>
