On Wed, Aug 7, 2024 at 3:24 PM Alvin Che-Chia Chang(張哲嘉) <alvi...@andestech.com> wrote: > > Hello Alistair, > > > -----Original Message----- > > From: Alistair Francis <alistai...@gmail.com> > > Sent: Wednesday, July 24, 2024 10:40 AM > > To: Alvin Che-Chia Chang(張哲嘉) <alvi...@andestech.com> > > Cc: qemu-ri...@nongnu.org; qemu-devel@nongnu.org; > > alistair.fran...@wdc.com; bin.m...@windriver.com; liwei1...@gmail.com; > > dbarb...@ventanamicro.com; zhiwei_...@linux.alibaba.com > > Subject: Re: [PATCH v3 0/2] RISC-V: Add preliminary textra trigger CSR > > functions > > > > [EXTERNAL MAIL] > > > > On Sun, Jul 21, 2024 at 5:26 PM Alvin Chang via <qemu-devel@nongnu.org> > > wrote: > > > > > > According to RISC-V Debug specification, the optional textra32 and > > > textra64 trigger CSRs can be used to configure additional matching > > > conditions for the triggers. > > > > > > This series support to write MHVALUE and MHSELECT fields into textra32 > > > and > > > textra64 trigger CSRs. Besides, the additional matching condition > > > between textra.MHVALUE and mcontext CSR is also implemented. > > > > > > Changes from v2: > > > - Remove redundant log > > > > > > Changes from v1: > > > - Log that mhselect only supports 0 or 4 for now > > > - Simplify writing of tdata3 > > > > > > Alvin Chang (2): > > > target/riscv: Preliminary textra trigger CSR writting support > > > target/riscv: Add textra matching condition for the triggers > > > > Thanks! > > > > Applied to riscv-to-apply.next > > I saw latest riscv-to-apply queue was submitted to qemu-devel yesterday. But > this series was not included. > Please allow me to inform this. Thanks!
Good catch! The PR yesterday was just fixing bugs for the upcoming release [1]. As this series isn't a bug fix I dropped it from the PR. It will be in the first PR for 9.2 though 1: https://wiki.qemu.org/Planning/9.1 Alistair
