On Fri, Aug 09, 2024 at 12:38:02AM -0700, Xin Li wrote:
> Date: Fri, 9 Aug 2024 00:38:02 -0700
> From: Xin Li <x...@zytor.com>
> Subject: Re: [PATCH v1 3/3] target/i386: Raise the highest index value used
> for any VMCS encoding
>
> On 8/8/2024 11:27 PM, Xin Li wrote:
> > > > + if (f[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED) {
> > > > + /* FRED injected-event data (0x2052). */
> > > > + kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x52);
> > >
> > > HMM, I have the questions when I check the FRED spec.
> > >
> > > Section 9.3.4 said, (for injected-event data) "This field has uses the
> > > encoding pair 2052H/2053H."
> > >
> > > So why adjust the highest index to 0x52 other than 0x53?
>
> Okay, found it in the Intel SDM:
>
> Index. Bits 9:1 distinguish components with the same field width and type.
>
> Bit 0 is not included in the index field.
Thanks for your education and explanation! I see, for
IA32_VMX_VMCS_ENUM, bit 0 is reserved and only index field is enough.
Regards,
Zhao
