From: TANG Tiancheng <tangtiancheng....@alibaba-inc.com> Add support for probing RISC-V vector extension availability in the backend. This information will be used when deciding whether to use vector instructions in code generation.
While the compiler doesn't support RISCV_HWPROBE_EXT_ZVE64X, we use RISCV_HWPROBE_IMA_V instead. Signed-off-by: TANG Tiancheng <tangtiancheng....@alibaba-inc.com> Reviewed-by: Liu Zhiwei <zhiwei_...@linux.alibaba.com> --- host/include/riscv/host/cpuinfo.h | 1 + util/cpuinfo-riscv.c | 20 ++++++++++++++++++-- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/host/include/riscv/host/cpuinfo.h b/host/include/riscv/host/cpuinfo.h index 2b00660e36..bf6ae51f72 100644 --- a/host/include/riscv/host/cpuinfo.h +++ b/host/include/riscv/host/cpuinfo.h @@ -10,6 +10,7 @@ #define CPUINFO_ZBA (1u << 1) #define CPUINFO_ZBB (1u << 2) #define CPUINFO_ZICOND (1u << 3) +#define CPUINFO_ZVE64X (1u << 4) /* Initialized with a constructor. */ extern unsigned cpuinfo; diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c index 497ce12680..551821edef 100644 --- a/util/cpuinfo-riscv.c +++ b/util/cpuinfo-riscv.c @@ -33,7 +33,7 @@ static void sigill_handler(int signo, siginfo_t *si, void *data) /* Called both as constructor and (possibly) via other constructors. */ unsigned __attribute__((constructor)) cpuinfo_init(void) { - unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND; + unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND | CPUINFO_ZVE64X; unsigned info = cpuinfo; if (info) { @@ -49,6 +49,9 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) #endif #if defined(__riscv_arch_test) && defined(__riscv_zicond) info |= CPUINFO_ZICOND; +#endif +#if defined(__riscv_arch_test) && defined(__riscv_zve64x) + info |= CPUINFO_ZVE64X; #endif left &= ~info; @@ -64,7 +67,8 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) && pair.key >= 0) { info |= pair.value & RISCV_HWPROBE_EXT_ZBA ? CPUINFO_ZBA : 0; info |= pair.value & RISCV_HWPROBE_EXT_ZBB ? CPUINFO_ZBB : 0; - left &= ~(CPUINFO_ZBA | CPUINFO_ZBB); + info |= pair.value & RISCV_HWPROBE_IMA_V ? CPUINFO_ZVE64X : 0; + left &= ~(CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZVE64X); #ifdef RISCV_HWPROBE_EXT_ZICOND info |= pair.value & RISCV_HWPROBE_EXT_ZICOND ? CPUINFO_ZICOND : 0; left &= ~CPUINFO_ZICOND; @@ -108,6 +112,18 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) left &= ~CPUINFO_ZICOND; } + if (left & CPUINFO_ZVE64X) { + /* Probe for Vector: vsetivli t0,1,e64,m1,ta,ma */ + unsigned vl; + got_sigill = 0; + + asm volatile( + "vsetivli %0, 1, e64, m1, ta, ma\n\t" + : "=r"(vl) : : "vl" + ); + info |= (got_sigill || vl != 1) ? 0 : CPUINFO_ZVE64X; + } + sigaction(SIGILL, &sa_old, NULL); assert(left == 0); } -- 2.43.0