On Sun, Aug 25, 2024 at 3:34 AM Daniel Henrique Barboza
<dbarb...@ventanamicro.com> wrote:
>
> Gitlab issue [1] reports a misleading error when trying to run a 'rv64'
> cpu with 'zfinx' and without 'f':
>
> $ ./build/qemu-system-riscv64 -nographic -M virt -cpu rv64,zfinx=true,f=false
> qemu-system-riscv64: Zfinx cannot be supported together with F extension
>
> The user explicitly disabled F and the error message mentions a conflict
> with Zfinx and F.
>
> The problem isn't the error reporting, but the logic used when applying
> the implied ZFA rule that enables RVF unconditionally, without honoring
> user choice (i.e. keep F disabled).
>
> Change cpu_enable_implied_rule() to check if the user deliberately
> disabled a MISA bit. In this case we shouldn't either re-enable the bit
> nor apply any implied rules related to it.
>
> After this change the error message now shows:
>
> $ ./build/qemu-system-riscv64 -nographic -M virt -cpu rv64,zfinx=true,f=false
> qemu-system-riscv64: Zfa extension requires F extension
>
> Disabling 'zfa':
>
> $ ./build/qemu-system-riscv64 -nographic -M virt -cpu
> rv64,zfinx=true,f=false,zfa=false
> qemu-system-riscv64: D extension requires F extension
>
> And finally after disabling 'd':
>
> $ ./build/qemu-system-riscv64 -nographic -M virt -cpu
> rv64,zfinx=true,f=false,zfa=false,d=false
> (OpenSBI boots ...)
>
> [1] https://gitlab.com/qemu-project/qemu/-/issues/2486
>
> Cc: Frank Chang <frank.ch...@sifive.com>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2486
> Fixes: 047da861f9 ("target/riscv: Introduce extension implied rule helpers")
> Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/tcg/tcg-cpu.c | 13 ++++++++++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index b8814ab753..dea8ab7a43 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -778,11 +778,18 @@ static void cpu_enable_implied_rule(RISCVCPU *cpu,
> if (!enabled) {
> /* Enable the implied MISAs. */
> if (rule->implied_misa_exts) {
> - riscv_cpu_set_misa_ext(env,
> - env->misa_ext | rule->implied_misa_exts);
> -
> for (i = 0; misa_bits[i] != 0; i++) {
> if (rule->implied_misa_exts & misa_bits[i]) {
> + /*
> + * If the user disabled the misa_bit do not re-enable it
> + * and do not apply any implied rules related to it.
> + */
> + if (cpu_misa_ext_is_user_set(misa_bits[i]) &&
> + !(env->misa_ext & misa_bits[i])) {
> + continue;
> + }
> +
> + riscv_cpu_set_misa_ext(env, env->misa_ext |
> misa_bits[i]);
> ir = g_hash_table_lookup(misa_ext_implied_rules,
> GUINT_TO_POINTER(misa_bits[i]));
>
> --
> 2.45.2
>
>
