On 10/10/24 07:35, Song Gao wrote:
+ base = get_pte_base(env, address);
+
+ /* 0:64bit, 1:128bit, 2:192bit, 3:256bit */
+ shift = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTEWIDTH);
+ shift = (shift + 1) * 3;
+ ptindex = (address >> ptbase) & ((1 << ptwidth) -1);
+ ptoffset = ptindex << shift;
+ tmp0 = base | ptoffset;
This is a guest virtual address.
+ retry:
+ old_val = ldq_phys(cs->as, tmp0) & TARGET_PHYS_MASK;
Fine.
+ if (old_val != new_val) {
+ cur_val = qatomic_cmpxchg((uint64_t *)tmp0, old_val, new_val);
This uses a host address. The cast, and the resulting reference, are incorrect.
This is why Arm and x86 structure things differently, using a different tlb index to
resolve the host address. This allows the result to be cached like any other address
resolution.
Riscv does something a bit simpler, using address_space_translate to resolve
the host address.
Most of the rest of this patch set is going to need review from loongson employees, since
I've not seen public documentation in english for this feature.
r~
