On Tue, Nov 12, 2024 at 07:10:36PM +0100, Philippe Mathieu-Daudé wrote: > Rather than accessing the registers within the mixed RAM/MMIO > region as indexed register, declare a per-port TX_GIE. This > will help to map the RAM as RAM (keeping MMIO as MMIO) in few > commits. > > Previous s->regs[R_TX_GIE0] and s->regs[R_TX_GIE1] are now > unused. Not a concern, this array will soon disappear.
Reviewed-by: Edgar E. Iglesias <[email protected]> > > Signed-off-by: Philippe Mathieu-Daudé <[email protected]> > --- > hw/net/xilinx_ethlite.c | 12 ++++++++++-- > 1 file changed, 10 insertions(+), 2 deletions(-) > > diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c > index 605451a522..4cb4781e70 100644 > --- a/hw/net/xilinx_ethlite.c > +++ b/hw/net/xilinx_ethlite.c > @@ -62,6 +62,8 @@ > typedef struct XlnxXpsEthLitePort > { > struct { > + uint32_t tx_gie; > + > uint32_t rx_ctrl; > } reg; > } XlnxXpsEthLitePort; > @@ -90,7 +92,7 @@ struct XlnxXpsEthLite > static inline void eth_pulse_irq(XlnxXpsEthLite *s) > { > /* Only the first gie reg is active. */ > - if (s->regs[R_TX_GIE0] & GIE_GIE) { > + if (s->port[0].reg.tx_gie & GIE_GIE) { > qemu_irq_pulse(s->irq); > } > } > @@ -126,6 +128,9 @@ eth_read(void *opaque, hwaddr addr, unsigned int size) > switch (addr) > { > case R_TX_GIE0: > + r = s->port[port_index].reg.tx_gie; > + break; > + > case R_TX_LEN0: > case R_TX_LEN1: > case R_TX_CTRL1: > @@ -189,10 +194,13 @@ eth_write(void *opaque, hwaddr addr, > > case R_TX_LEN0: > case R_TX_LEN1: > - case R_TX_GIE0: > s->regs[addr] = value; > break; > > + case R_TX_GIE0: > + s->port[port_index].reg.tx_gie = value; > + break; > + > default: > s->regs[addr] = tswap32(value); > break; > -- > 2.45.2 >
