Hi all,
According to the MIPS documentation, the K0 bits in Config0 should be
writable by the software. Currently QEMU only allow to write the low
bit of this field which has three bits. Even if this value is ignored by
QEMU, it should be writable the same way as on real hardware. At least
it should allow to write the two values required, ie '2' and '3'.
The patch below fixes that.
Bye,
Aurelien
Index: target-mips/op.c
===================================================================
RCS file: /sources/qemu/qemu/target-mips/op.c,v
retrieving revision 1.65
diff -u -d -p -r1.65 op.c
--- target-mips/op.c 29 May 2007 16:52:56 -0000 1.65
+++ target-mips/op.c 10 Jun 2007 09:47:53 -0000
@@ -1433,7 +1440,7 @@ void op_mtc0_ebase (void)
void op_mtc0_config0 (void)
{
- env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (T0 & 0x00000001);
+ env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (T0 & 0x00000007);
RETURN();
}
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' [EMAIL PROTECTED] | [EMAIL PROTECTED]
`- people.debian.org/~aurel32 | www.aurel32.net
