Sorry for the quick repost. Changes since v9: - Add element-wise loop to handle case where no suitable atomic operation is available.
Changes since v8: - Add missing CONFIG_ATOMIC64 guard. Previous versions: - v1: https://lore.kernel.org/all/[email protected]/ - v2: https://lore.kernel.org/all/[email protected]/ - v3: https://lore.kernel.org/all/[email protected]/ - v4: https://lore.kernel.org/all/[email protected]/ - v5: https://lore.kernel.org/all/[email protected]/ - v6: https://lore.kernel.org/all/[email protected]/ - v7: https://lore.kernel.org/all/[email protected]/ - v8: https://lore.kernel.org/all/[email protected]/ - v9: https://lore.kernel.org/all/[email protected]/ Cc: Richard Henderson <[email protected]> Cc: Palmer Dabbelt <[email protected]> Cc: Alistair Francis <[email protected]> Cc: Bin Meng <[email protected]> Cc: Weiwei Li <[email protected]> Cc: Daniel Henrique Barboza <[email protected]> Cc: Liu Zhiwei <[email protected]> Cc: Helene Chelin <[email protected]> Cc: Nathan Egge <[email protected]> Cc: Max Chou <[email protected]> Craig Blackmore (1): target/riscv: rvv: Use wider accesses for unit stride load/store target/riscv/vector_helper.c | 95 +++++++++++++++++++++++++++++++++--- 1 file changed, 87 insertions(+), 8 deletions(-) -- 2.43.0
