Propagate the target agnostic CPU pointer to the publicly declared bl_gen_write_u32() function.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- include/hw/mips/bootloader.h | 3 ++- hw/mips/bootloader.c | 9 +++++---- hw/mips/malta.c | 18 +++++++++--------- 3 files changed, 16 insertions(+), 14 deletions(-) diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h index a7f174e16bc..cc2ffe3ab2c 100644 --- a/include/hw/mips/bootloader.h +++ b/include/hw/mips/bootloader.h @@ -22,7 +22,8 @@ void bl_gen_jump_kernel(const MIPSCPU *cpu, void **ptr, target_ulong kernel_addr); void bl_gen_write_ulong(const MIPSCPU *cpu, void **ptr, target_ulong addr, target_ulong val); -void bl_gen_write_u32(void **ptr, target_ulong addr, uint32_t val); +void bl_gen_write_u32(const MIPSCPU *cpu, void **ptr, + target_ulong addr, uint32_t val); void bl_gen_write_u64(void **ptr, target_ulong addr, uint64_t val); #endif diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index c4fd85b9f42..6f0222faf48 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -295,11 +295,12 @@ void bl_gen_write_ulong(const MIPSCPU *cpu, void **p, } } -void bl_gen_write_u32(void **p, target_ulong addr, uint32_t val) +void bl_gen_write_u32(const MIPSCPU *cpu, void **p, + target_ulong addr, uint32_t val) { - bl_gen_li(&MIPS_CPU(first_cpu)->env, p, BL_REG_K0, val); - bl_gen_load_ulong(&MIPS_CPU(first_cpu)->env, p, BL_REG_K1, addr); - bl_gen_sw(&MIPS_CPU(first_cpu)->env, p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_li(&cpu->env, p, BL_REG_K0, val); + bl_gen_load_ulong(&cpu->env, p, BL_REG_K1, addr); + bl_gen_sw(&cpu->env, p, BL_REG_K0, BL_REG_K1, 0x0); } void bl_gen_write_u64(void **p, target_ulong addr, uint64_t val) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index fe9e06f48f4..5ccff2cb0c1 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -636,29 +636,29 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, /* setup MEM-to-PCI0 mapping as done by YAMON */ /* move GT64120 registers from 0x14000000 to 0x1be00000 */ - bl_gen_write_u32(p, /* GT_ISD */ + bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_ISD */ cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68), cpu_to_gt32(0x1be00000 << 3)); /* setup PCI0 io window to 0x18000000-0x181fffff */ - bl_gen_write_u32(p, /* GT_PCI0IOLD */ + bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_PCI0IOLD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48), cpu_to_gt32(0x18000000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0IOHD */ + bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_PCI0IOHD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50), cpu_to_gt32(0x08000000 << 3)); /* setup PCI0 mem windows */ - bl_gen_write_u32(p, /* GT_PCI0M0LD */ + bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_PCI0M0LD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58), cpu_to_gt32(0x10000000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0M0HD */ + bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_PCI0M0HD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60), cpu_to_gt32(0x07e00000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0M1LD */ + bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_PCI0M1LD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80), cpu_to_gt32(0x18200000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0M1HD */ + bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_PCI0M1HD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88), cpu_to_gt32(0x0bc00000 << 3)); @@ -669,12 +669,12 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, * Load the PIIX IRQC[A:D] routing config address, then * write routing configuration to the config data register. */ - bl_gen_write_u32(p, /* GT_PCI0_CFGADDR */ + bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_PCI0_CFGADDR */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8), tswap32((1 << 31) /* ConfigEn */ | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8 | PIIX_PIRQCA)); - bl_gen_write_u32(p, /* GT_PCI0_CFGDATA */ + bl_gen_write_u32(MIPS_CPU(first_cpu), p, /* GT_PCI0_CFGDATA */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc), tswap32(ldl_be_p(pci_pins_cfg))); -- 2.47.1
