On Tue, Apr 24, 2012 at 03:46:25PM +0200, Paolo Bonzini wrote: > Il 23/04/2012 15:19, Michael S. Tsirkin ha scritto: [snip] > > #elif defined(_ARCH_PPC) > > > > /* > > - * We use an eieio() for a wmb() on powerpc. This assumes we don't > > + * We use an eieio() for wmb() and mb() on powerpc. This assumes we don't > > * need to order cacheable and non-cacheable stores with respect to > > * each other > > */ > > #define smp_wmb() asm volatile("eieio" ::: "memory") > > +#define smp_mb() asm volatile("eieio" ::: "memory") > > smp_mb() is hwsync under PPC, but I would just trust GCC.
I assume you mean 'lwsync', no such thing as 'hwsync', afaik. And I assume you're talking about the kernel here. So, the situation in qemu is different from in the kernel, because as far as I know there's no case in qemu where we need to synchronize cacheable stores with non-cacheable (I/O) stores. eieio won't do that, but it will order cacheable stores w.r.t. other cacheable stores. I think __sync_synchronize() will be a 'sync', the most heavyweight memory barrier on ppc. -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson