[PATCH 13/38] target/hexagon: Define DCache states

[Brian Cain]

From: Brian Cain <bc...@quicinc.com>

Signed-off-by: Brian Cain <brian.c...@oss.qualcomm.com>
---
 target/hexagon/cpu_bits.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h
index 6582bb4f16..5d26815eb9 100644
--- a/target/hexagon/cpu_bits.h
+++ b/target/hexagon/cpu_bits.h
@@ -41,6 +41,13 @@ enum hex_cause {
     HEX_CAUSE_PRIV_USER_NO_SINSN = 0x01b,
 };
 
+enum data_cache_state {
+    HEX_DC_STATE_INVALID   = 0x0,
+    HEX_DC_STATE_VALID     = 0x1,
+    HEX_DC_STATE_RESERVED  = 0x2,
+    HEX_DC_STATE_UNUSED_WT = 0x3,
+};
+
 #define PACKET_WORDS_MAX         4
 
 static inline uint32_t parse_bits(uint32_t encoding)
-- 
2.34.1