The following changes since commit 661c2e1ab29cd9c4d268ae3f44712e8d421c0e56:
scripts/checkpatch: Fix a typo (2025-03-04 09:30:26 +0800) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20250305-1 for you to fetch changes up to 4db19d5b21e058e6eb3474b6be470d1184afaa9e: target/riscv/kvm: add missing KVM CSRs (2025-03-04 15:42:54 +1000) ---------------------------------------------------------------- Third RISC-V PR for 10.0 * CSR coverity fixes * Fix unexpected behavior of vector reduction instructions when vl is 0 * Fix incorrect vlen comparison in prop_vlen_set * Throw debug exception before page fault * Remove redundant "hart_idx" masking from APLIC * Add support for Control Transfer Records Ext * Remove redundant struct members from the IOMMU * Remove duplicate definitions from the IOMMU * Fix tick_offset migration for Goldfish RTC * Add serial alias in virt machine DTB * Remove Bin Meng from RISC-V maintainers * Add support for Control Transfer Records Ext * Log guest errors when reserved bits are set in PTEs * Add missing Sdtrig disas CSRs * Correct the hpmevent sscofpmf mask * Mask upper sscofpmf bits during validation * Remove warnings about Smdbltrp/Smrnmi being disabled * Respect mseccfg.RLB bit for TOR mode PMP entry * Update KVM support to Linux 6.14-rc3 * IOMMU HPM support * Support Sscofpmf/Svade/Svadu/Smnpm/Ssnpm extensions in KVM * Add --ignore-family option to binfmt * Refinement for AIA with KVM acceleration * Reset time changes for KVM ---------------------------------------------------------------- Alistair Francis (1): MAINTAINERS: Remove Bin Meng from RISC-V maintainers Andrea Bolognani (3): binfmt: Shuffle things around binfmt: Normalize host CPU architecture binfmt: Add --ignore-family option Atish Patra (2): target/riscv: Fix the hpmevent mask target/riscv: Mask out upper sscofpmf bits during validation Clément Léger (1): target/riscv: remove warnings about Smdbltrp/Smrnmi being disabled Daniel Henrique Barboza (22): target/riscv/csr.c: fix deadcode in rmw_xireg() target/riscv/csr.c: fix 'ret' deadcode in rmw_xireg() target/riscv/csr.c: fix deadcode in rmw_xiregi() target/riscv/csr.c: fix deadcode in aia_smode32() target/riscv/cpu_helper.c: fix bad_shift in riscv_cpu_interrupt() target/riscv/debug.c: use wp size = 4 for 32-bit CPUs target/riscv: throw debug exception before page fault target/riscv: add ssu64xl target/riscv: use RVB in RVA22U64 target/riscv: add profile u_parent and s_parent target/riscv: change priv_ver check in validate_profile() target/riscv: add RVA23U64 profile target/riscv: add RVA23S64 profile linux-headers: Update to Linux v6.14-rc3 target/riscv/cpu.c: create flag for ziccrse target/riscv/kvm: add extensions after 6.14-rc3 update hw/riscv/riscv-iommu.h: add missing headers hw/riscv: add IOMMU HPM trace events docs/specs/riscv-iommu.rst: add HPM support info target/riscv/cpu: remove unneeded !kvm_enabled() check target/riscv/kvm: add kvm_riscv_reset_regs_csr() target/riscv/kvm: add missing KVM CSRs Huang Borong (1): hw/intc/riscv_aplic: Remove redundant "hart_idx" masking Jason Chien (2): hw/riscv/riscv-iommu: Remove redundant struct members hw/riscv/riscv-iommu-bits: Remove duplicate definitions Max Chou (2): target/riscv: rvv: Fix unexpected behavior of vector reduction instructions when vl is 0 target/riscv: rvv: Fix incorrect vlen comparison in prop_vlen_set Quan Zhou (1): target/riscv/kvm: Add some exts support Rajnesh Kanwal (7): target/riscv: Remove obsolete sfence.vm instruction target/riscv: Add Control Transfer Records CSR definitions. target/riscv: Add support for Control Transfer Records extension CSRs. target/riscv: Add support to record CTR entries. target/riscv: Add CTR sctrclr instruction. target/riscv: machine: Add Control Transfer Record state description target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs. Rob Bradford (3): disas/riscv: Fix minor whitespace issues disas/riscv: Add missing Sdtrig CSRs target/riscv: Respect mseccfg.RLB bit for TOR mode PMP entry Rodrigo Dias Correa (1): goldfish_rtc: Fix tick_offset migration Tomasz Jeznach (8): hw/riscv/riscv-iommu-bits.h: HPM bits hw/riscv/riscv-iommu: add riscv-iommu-hpm file hw/riscv/riscv-iommu: add riscv_iommu_hpm_incr_ctr() hw/riscv/riscv-iommu: instantiate hpm_timer hw/riscv/riscv-iommu: add IOCOUNTINH mmio writes hw/riscv/riscv-iommu: add IOHPMCYCLES mmio write hw/riscv/riscv-iommu: add hpm events mmio write hw/riscv/riscv-iommu.c: add RISCV_IOMMU_CAP_HPM cap Vasilis Liaskovitis (1): hw/riscv/virt: Add serial alias in DTB Yong-Xuan Wang (3): hw/intc/imsic: refine the IMSIC realize hw/intc/aplic: refine the APLIC realize hw/intc/aplic: refine kvm_msicfgaddr julia (1): target/riscv: log guest errors when reserved bits are set in PTEs MAINTAINERS | 5 +- docs/specs/riscv-iommu.rst | 2 + hw/riscv/riscv-iommu-bits.h | 69 +++- hw/riscv/riscv-iommu-hpm.h | 33 ++ hw/riscv/riscv-iommu.h | 32 +- include/standard-headers/linux/ethtool.h | 4 + include/standard-headers/linux/fuse.h | 76 +++- include/standard-headers/linux/input-event-codes.h | 1 + include/standard-headers/linux/pci_regs.h | 16 +- include/standard-headers/linux/virtio_pci.h | 14 + linux-headers/asm-arm64/kvm.h | 3 - linux-headers/asm-loongarch/kvm_para.h | 1 + linux-headers/asm-riscv/kvm.h | 7 +- linux-headers/asm-x86/kvm.h | 1 + linux-headers/linux/iommufd.h | 35 +- linux-headers/linux/kvm.h | 8 +- linux-headers/linux/stddef.h | 13 +- linux-headers/linux/vduse.h | 2 +- target/riscv/cpu-qom.h | 2 + target/riscv/cpu.h | 16 +- target/riscv/cpu_bits.h | 150 +++++++- target/riscv/cpu_cfg.h | 5 + target/riscv/helper.h | 2 + target/riscv/insn32.decode | 2 +- disas/riscv.c | 16 +- hw/intc/riscv_aplic.c | 74 ++-- hw/intc/riscv_imsic.c | 47 +-- hw/riscv/riscv-iommu-hpm.c | 381 +++++++++++++++++++++ hw/riscv/riscv-iommu.c | 131 ++++++- hw/riscv/virt.c | 3 + hw/rtc/goldfish_rtc.c | 43 +-- target/riscv/cpu.c | 115 ++++++- target/riscv/cpu_helper.c | 315 ++++++++++++++++- target/riscv/csr.c | 318 +++++++++++++++-- target/riscv/debug.c | 6 +- target/riscv/kvm/kvm-cpu.c | 40 ++- target/riscv/machine.c | 25 ++ target/riscv/op_helper.c | 48 +++ target/riscv/pmp.c | 2 +- target/riscv/pmu.c | 2 +- target/riscv/tcg/tcg-cpu.c | 58 +++- target/riscv/translate.c | 46 +++ target/riscv/vector_helper.c | 8 +- target/riscv/insn_trans/trans_privileged.c.inc | 18 +- target/riscv/insn_trans/trans_rvi.c.inc | 75 ++++ target/riscv/insn_trans/trans_rvzce.c.inc | 21 ++ hw/riscv/meson.build | 3 +- hw/riscv/trace-events | 5 + scripts/qemu-binfmt-conf.sh | 78 +++-- tests/data/acpi/riscv64/virt/RHCT | Bin 390 -> 400 bytes 50 files changed, 2106 insertions(+), 271 deletions(-) create mode 100644 hw/riscv/riscv-iommu-hpm.h create mode 100644 hw/riscv/riscv-iommu-hpm.c
