On Fri, Feb 28, 2025 at 8:31 PM Paolo Bonzini <[email protected]> wrote: > > From: Philippe Mathieu-Daudé <[email protected]> > > Signed-off-by: Philippe Mathieu-Daudé <[email protected]> > Reviewed-by: Richard Henderson <[email protected]> > Link: https://lore.kernel.org/r/[email protected] > Signed-off-by: Paolo Bonzini <[email protected]>
Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > target/riscv/cpu.h | 2 +- > target/riscv/cpu.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index df7a05e7d15..3041a4be5c9 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -543,7 +543,7 @@ struct RISCVCPUClass { > > DeviceRealize parent_realize; > ResettablePhases parent_phases; > - uint32_t misa_mxl_max; /* max mxl for this cpu */ > + RISCVMXL misa_mxl_max; /* max mxl for this cpu */ > }; > > static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 244e44ce410..85dc2fe3bec 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -2961,7 +2961,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void > *data) > { > RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); > > - mcc->misa_mxl_max = (uint32_t)(uintptr_t)data; > + mcc->misa_mxl_max = (RISCVMXL)(uintptr_t)data; > riscv_cpu_validate_misa_mxl(mcc); > } > > -- > 2.48.1 > >
