RE: [PATCH 08/38] target/hexagon: Add guest, system reg number defs

[Sid Manning]

> -----Original Message-----
> From: ltaylorsimp...@gmail.com <ltaylorsimp...@gmail.com>
> Sent: Thursday, March 6, 2025 3:30 PM
> To: 'Brian Cain' <brian.c...@oss.qualcomm.com>; qemu-devel@nongnu.org
> Cc: richard.hender...@linaro.org; phi...@linaro.org; Matheus Bernardino
> (QUIC) <quic_mathb...@quicinc.com>; a...@rev.ng; a...@rev.ng; Marco
> Liebel (QUIC) <quic_mlie...@quicinc.com>; alex.ben...@linaro.org; Mark
> Burton (QUIC) <quic_mbur...@quicinc.com>; Sid Manning
> <sidn...@quicinc.com>; Brian Cain <bc...@quicinc.com>
> Subject: RE: [PATCH 08/38] target/hexagon: Add guest, system reg number
> defs
> 
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> > -----Original Message-----
> > From: Brian Cain <brian.c...@oss.qualcomm.com>
> > Sent: Friday, February 28, 2025 11:26 PM
> > To: qemu-devel@nongnu.org
> > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng;
> a...@rev.ng;
> > quic_mlie...@quicinc.com; ltaylorsimp...@gmail.com;
> > alex.ben...@linaro.org; quic_mbur...@quicinc.com;
> sidn...@quicinc.com;
> > Brian Cain <bc...@quicinc.com>
> > Subject: [PATCH 08/38] target/hexagon: Add guest, system reg number
> > defs
> >
> > From: Brian Cain <bc...@quicinc.com>
> >
> > These registers are defined in the Qualcomm Hexagon V71 Programmer's
> > Reference Manual -
> https://docs.qualcomm.com/bundle/publicresource/80-
> > N2040-51_REV_AB_Hexagon_V71_ProgrammerS_Reference_Manual.pdf
> > Refer to §11.9.1 SYSTEM GUEST, §11.9.2 SYSTEM MONITOR.
> 
> Strange to put this in the checkin description.  See prior conversation about
> doc references.
> 
> >
> > Signed-off-by: Brian Cain <brian.c...@oss.qualcomm.com>
> > ---
> >  target/hexagon/cpu.h      |   5 ++
> >  target/hexagon/hex_regs.h | 115
> > ++++++++++++++++++++++++++++++++++++++
> >  2 files changed, 120 insertions(+)
> >
> > diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index
> > 79e60d4bfa..20ea0adcca 100644
> > --- a/target/hexagon/cpu.h
> > +++ b/target/hexagon/cpu.h
> > @@ -20,6 +20,11 @@
> >
> >  #include "fpu/softfloat-types.h"
> >
> > +#define NUM_GREGS 32
> > +#define GREG_WRITES_MAX 32
> 
> Can you actually write 32 G registers in a single packet?
> 
> > +#define NUM_SREGS 64
> > +#define SREG_WRITES_MAX 64
> 
> Ditto
[Sid Manning] 
Based on packet constraints the max for GREGS and SREGS would be 2.
In addition, REG_WRITES_MAX should be 10 not 32, 4 pairs + sa0/lc0 when the 
packet has an endloop.

> 
> > +
> >  #include "cpu-qom.h"
> >  #include "exec/cpu-defs.h"
> >  #include "hex_regs.h"
>