On 3/7/25 5:39 PM, Jason Chien wrote:
When the IOMMU detects that bus->iommu_ops has been registered, indicating
the presence of an ATU, it sets the bus's downstream memory region to ensure
transactions are directed to the IOMMU.
Signed-off-by: Jason Chien <[email protected]>
---
Reviewed-by: Daniel Henrique Barboza <[email protected]>
hw/riscv/riscv-iommu.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index d46beb2d64..9701fe3831 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -2628,11 +2628,16 @@ static const PCIIOMMUOps riscv_iommu_ops = {
void riscv_iommu_pci_setup_iommu(RISCVIOMMUState *iommu, PCIBus *bus,
Error **errp)
{
- if (bus->iommu_ops &&
- bus->iommu_ops->get_address_space == riscv_iommu_find_as) {
- /* Allow multiple IOMMUs on the same PCIe bus, link known devices */
- RISCVIOMMUState *last = (RISCVIOMMUState *)bus->iommu_opaque;
- QLIST_INSERT_AFTER(last, iommu, iommus);
+ if (bus->iommu_ops) {
+ if (bus->iommu_ops->get_address_space == riscv_iommu_find_as) {
+ /* Allow multiple IOMMUs on the same PCIe bus, link known devices
*/
+ RISCVIOMMUState *last = (RISCVIOMMUState *)bus->iommu_opaque;
+ QLIST_INSERT_AFTER(last, iommu, iommus);
+ } else {
+ /* The bus has an ATU. Set its downsteam memory region. */
+ AddressSpace *as = riscv_iommu_space(iommu, 0);
+ pci_setup_iommu_downstream_mr(bus, as->root);
+ }
} else if (!bus->iommu_ops && !bus->iommu_opaque) {
pci_setup_iommu(bus, &riscv_iommu_ops, iommu);
} else {
