From: Santiago Monserrat Campanello <[email protected]> semihosting link to risc-v changed
Signed-off-by: Santiago Monserrat Campanello <[email protected]> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2717 Reviewed-by: Alistair Francis <[email protected]> Reviewed-by: Thomas Huth <[email protected]> Message-ID: <[email protected]> Signed-off-by: Alistair Francis <[email protected]> (cherry picked from commit 672cb29d1e811180bf1aeefbcb0936ecd5bd3853) Signed-off-by: Michael Tokarev <[email protected]> diff --git a/docs/about/emulation.rst b/docs/about/emulation.rst index 3028d5fff7..951f5ae1c4 100644 --- a/docs/about/emulation.rst +++ b/docs/about/emulation.rst @@ -171,7 +171,7 @@ for that architecture. - Unified Hosting Interface (MD01069) * - RISC-V - System and User-mode - - https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc + - https://github.com/riscv-non-isa/riscv-semihosting/blob/main/riscv-semihosting.adoc * - Xtensa - System - Tensilica ISS SIMCALL -- 2.39.5
