Hi Dongli,
I noticed you've sent the V3 patchset, but I believe it's more appropriate to
continue the discussion about the issues you encountered in this thread.
On 3/29/25 12:42 AM, Dongli Zhang wrote:
The vendor and CPU are different. i.e., if we use Zhaoxin CPU without
configuring vendor: "-cpu YongFeng,+pmu \" on Intel KVM.
The CPU is Zhaoxin while vendor is still Intel.
[1] QEMU always sets the vCPU's vendor to match the host's vendor when
acceleration (KVM or HVF) is enabled(except for users set guest vendor
with -cpu xx, vendor=xx).
The PMU selection is based on vendor, not CPU.
[ 0.321163] smpboot: CPU0: Intel Zhaoxin YongFeng Processor (family: 0x7,
model: 0xb, stepping: 0x3)
[ 0.321996] Performance Events: generic architected perfmon, Intel PMU
driver.
[ 0.322867] ... version: 2
[ 0.323738] ... bit width: 48
[ 0.323864] ... generic registers: 4
[ 0.324776] ... value mask: 0000ffffffffffff
[ 0.324864] ... max period: 000000007fffffff
[ 0.325864] ... fixed-purpose events: 3
[ 0.326749] ... event mask: 000000070000000f
By default, IS_INTEL_CPU() still returns true even we emulate Zhaoxin on Intel
KVM.
[2] As mentioned in [1], QEMU always sets the vCPU's vendor to match the host's
vendor
when acceleration (KVM or HVF) is enabled. Therefore, if users want to emulate a
Zhaoxin CPU on an Intel host, the vendor must be set manually.Furthermore,
should we display a warning to users who enable both vPMU and KVM acceleration
but do not manually set the guest vendor when it differs from the host vendor?
I did many efforts, and I could not use Zhaoxin's PMU on Intel hypervisor.
According to arch/x86/events/zhaoxin/core.c, the Zhaoxin's PMU is working in
limited conditions, especially only when stepping >= 0xe.
switch (boot_cpu_data.x86) {
case 0x06:
/*
* Support Zhaoxin CPU from ZXC series, exclude Nano series through FMS.
* Nano FMS: Family=6, Model=F, Stepping=[0-A][C-D]
* ZXC FMS: Family=6, Model=F, Stepping=E-F OR Family=6, Model=0x19,
Stepping=0-3
*/
if ((boot_cpu_data.x86_model == 0x0f && boot_cpu_data.x86_stepping >=
0x0e) ||
boot_cpu_data.x86_model == 0x19) {
From QEMU, the stepping of YongFeng is always 3.
5502 .name = "YongFeng",
5503 .level = 0x1F,
5504 .vendor = CPUID_VENDOR_ZHAOXIN1,
5505 .family = 7,
5506 .model = 11,
5507 .stepping = 3,
Therefore, I cannot enable Zhaoxin's PMU on Intel KVM.
-cpu YongFeng,vendor="CentaurHauls",+pmu \
[ 0.253229] smpboot: CPU0: Centaur Zhaoxin YongFeng Processor (family: 0x7,
model: 0xb, stepping: 0x3)
[ 0.254009] Performance Events:
[ 0.254009] core: Welcome to zhaoxin pmu!
[ 0.254880] core: Version check pass!
[ 0.255567] no PMU driver, software events only.
It doesn't work on Intel Icelake hypervisor too, even with "host".
-cpu host,vendor="CentaurHauls",+pmu \
[ 0.268434] smpboot: CPU0: Centaur Intel(R) Xeon(R) Gold 6354 CPU @ 3.00GHz
(family: 0x6, model: 0x6a, stepping: 0x6)
[ 0.269237] Performance Events:
[ 0.269237] core: Welcome to zhaoxin pmu!
[ 0.270112] core: Version check pass!
[ 0.270768] no PMU driver, software events only.
The PMU never works, although cpuid returns PMU config.
[root@vm ~]# cpuid -1 -l 0xa
CPU:
Architecture Performance Monitoring Features (0xa):
version ID = 0x2 (2)
number of counters per logical processor = 0x8 (8)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x8 (8)
core cycle event = available
instruction retired event = available
reference cycles event = available
last-level cache ref event = available
last-level cache miss event = available
branch inst retired event = available
branch mispred retired event = available
top-down slots event = available
... ...
number of contiguous fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = true
So far I am not able to use Zhaoxin PMU on Intel hypervisor.
Since I don't have Zhaoxin environment, I am not sure about "vice versa".
Unless there is more suggestion from Zhao, I may replace is_same_vendor() with
vendor_compatible().
I'm sorry I didn't provide you with enough information about the Zhaoxin PMU.
1. I made a mistake in the Zhaoxin YongFeng vCPU model patch. The correct model
should be 0x5b, but I mistakenly set it to 0xb (11). The mistake happened
because
I overlooked the extended model bits from cpuid[eax=0x1].eax and only used the
base model. I'll send a fix patch soon.
2. As you can see in zhaoxin_pmu_init() in the Linux kernel, there is no
handling
for CPUs with family 0x7 and model (base + extended) 0x5b. The reason is clear:
we submitted a patch for zhaoxin_pmu_init() to support YongFeng two years ago
(https://lore.kernel.org/lkml/[email protected]/),
but received no response. We will keep trying to resubmit it.
