Re: [PATCH v2 06/12] target/riscv: rvv: Apply vext_check_input_eew to OPIVV/OPFVV(vext_check_sss) instructions

[Daniel Henrique Barboza]

On 3/29/25 11:44 AM, Max Chou wrote:

Handle the overlap of source registers with different EEWs.

Co-authored-by: Anton Blanchard <ant...@tenstorrent.com>
Co-authored-by: Max Chou <max.c...@sifive.com>
Signed-off-by: Max Chou <max.c...@sifive.com>
---

With your co-authored-by tag removed:

Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>

  target/riscv/insn_trans/trans_rvv.c.inc | 1 +
  1 file changed, 1 insertion(+)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index 3d02a2f9ec8..2282b89801c 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -433,6 +433,7 @@ static bool vext_check_ss(DisasContext *s, int vd, int vs, 
int vm)
  static bool vext_check_sss(DisasContext *s, int vd, int vs1, int vs2, int vm)
  {
      return vext_check_ss(s, vd, vs2, vm) &&
+           vext_check_input_eew(s, vs1, s->sew, vs2, s->sew, vm) &&
             require_align(vs1, s->lmul);
  }