This patch series fixes several corner cases of RISC-V vector
instruction's encoding constraints.
This v3 series addresses:
- Merge v2 patches (3 & 4, 9 & 10)
- Remove extra blank line in v2 patch 5
- Remove redundant co-authored-by tags
Thank for Daniel Henrique Barboza's suggestions and review.
Anton Blanchard (2):
target/riscv: rvv: Source vector registers cannot overlap mask
register
target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS
Max Chou (8):
target/riscv: rvv: Apply vext_check_input_eew to vrgather instructions
to check mismatched input EEWs encoding constraint
target/riscv: rvv: Apply vext_check_input_eew to
OPIVI/OPIVX/OPFVF(vext_check_ss) instructions
target/riscv: rvv: Apply vext_check_input_eew to
OPIVV/OPFVV(vext_check_sss) instructions
target/riscv: rvv: Apply vext_check_input_eew to vector slide
instructions(OPIVI/OPIVX)
target/riscv: rvv: Apply vext_check_input_eew to vector integer
extension instructions(OPMVV)
target/riscv: rvv: Apply vext_check_input_eew to vector narrow/widen
instructions
target/riscv: rvv: Apply vext_check_input_eew to vector indexed
load/store instructions
target/riscv: Fix the rvv reserved encoding of unmasked instructions
target/riscv/insn32.decode | 18 +--
target/riscv/insn_trans/trans_rvbf16.c.inc | 9 +-
target/riscv/insn_trans/trans_rvv.c.inc | 166 +++++++++++++++++----
3 files changed, 153 insertions(+), 40 deletions(-)
--
2.43.0
