On 10 May 2012 09:10, 陳韋任 <che...@iis.sinica.edu.tw> wrote: > I see only x86 define TARGET_HAS_PRECISE_SMC (target-i386/cpu.h), and the > comment says, > > /* support for self modifying code even if the modified instruction is > close to the modifying instruction */ > #define TARGET_HAS_PRECISE_SMC > > I would like to know what it means and want to know more about it, but > googling doesn't help. Would you mind to shed some light on that? Thanks.
This enables support for handling the case where a guest instruction modifies the memory corresponding to the QEMU TB which it is in. For most CPU architectures this will (on hardware) give unpredictable results because of hardware prefetch / pipelining / caching, and so there's no need for QEMU to go to great lengths to support it (typically the CPU architecture requires some explicit act like a cache flush before starting to execute the modified code, which is where QEMU will flush its translation cache). On x86 actions like "modify the next instruction" have historically worked and so QEMU has to actually handle this. -- PMM
