On Mon, 2012-05-14 at 19:52 -0500, Anthony Liguori wrote: > > > > diff --git a/dma-helpers.c b/dma-helpers.c > > index 36fa963..4350cdf 100644 > > --- a/dma-helpers.c > > +++ b/dma-helpers.c > > @@ -312,6 +312,9 @@ int iommu_dma_memory_rw(DMAContext *dma, dma_addr_t > > addr, > > buf += plen; > > } > > > > + /* HACK: full memory barrier here */ > > + __sync_synchronize(); > > I thought you were going to limit this to the TCE iommu?
I can I suppose but technically speaking, this isn't an attribute of the iommu... in fact, from a model standpoint, it should be in the pci_* accessors since PCI transactions are ordered (at least to some extent, let's not get into relaxed ordering etc... at this stage). It was just easier to stick it in the above function for now, which handles all known cases... I'm happy to move it to the TCE backend if you prefer for now but I can see that problem hitting other architectures such as ARM or even on powerpc, hitting emulated PCI on Alex "usermode" KVM using the Mac99 machine model which doesn't use TCEs etc.... Cheers, Ben.
