On Thu, May 29, 2025 at 02:48:28PM +0100, Jonathan Cameron wrote:
> This has been wrong from day 1. For now we only have
> two entries (component and device registers).
>
> The wrong size could lead to arbitrary data off the stack being presented
> in PCIe config space.
>
> Signed-off-by: Jonathan Cameron <jonathan.came...@huawei.com>
> ---
Reviewed-by: Fan Ni <fan...@samsung.com>
> include/hw/cxl/cxl_pci.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/hw/cxl/cxl_pci.h b/include/hw/cxl/cxl_pci.h
> index d0855ed78b..3bb882ce89 100644
> --- a/include/hw/cxl/cxl_pci.h
> +++ b/include/hw/cxl/cxl_pci.h
> @@ -31,7 +31,7 @@
> #define PCIE_CXL3_FLEXBUS_PORT_DVSEC_LENGTH 0x20
> #define PCIE_CXL3_FLEXBUS_PORT_DVSEC_REVID 2
>
> -#define REG_LOC_DVSEC_LENGTH 0x24
> +#define REG_LOC_DVSEC_LENGTH 0x1C
> #define REG_LOC_DVSEC_REVID 0
>
> enum {
> --
> 2.48.1
>
--
Fan Ni (From gmail)
