On Wed, May 16, 2012 at 09:28:39PM -0500, Anthony Liguori wrote:
> On 05/16/2012 07:52 PM, Benjamin Herrenschmidt wrote:
[snip]
> >@@ -2794,6 +2795,9 @@ void *qemu_get_ram_ptr(ram_addr_t addr)
> > {
> > RAMBlock *block;
> >
> >+ /* We ensure ordering for all DMA transactions */
> >+ dma_mb();
> >+
>
> I get being conservative, but I don't think this makes a lot of
> sense. There are cases where the return of this function is cached
> (like the VGA ram area). I think it would make more sense if you
> explicitly put a barrier after write operations.
I tend to agree. I think the barriers should be in
cpu_physical_memory_rw() and the st*_phys() functions.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
