Move below instructions to decodetree specification:
f{mr, neg, abs, nabs} : X-form
The changes were verified by validating that the tcg ops generated by
those instructions remain the same, which were captured with the '-d
in_asm,op' flag.
Signed-off-by: Chinmay Rath <ra...@linux.ibm.com>
---
target/ppc/insn32.decode | 7 +++
target/ppc/translate/fp-impl.c.inc | 80 ++++++++----------------------
target/ppc/translate/fp-ops.c.inc | 4 --
3 files changed, 28 insertions(+), 63 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 0ffd814471..abbdb9fd82 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -503,6 +503,13 @@ STFDU 110111 ..... ...... ............... @D
STFDX 011111 ..... ...... .... 1011010111 - @X
STFDUX 011111 ..... ...... .... 1011110111 - @X
+### Floating-Point Move Instructions
+
+FMR 111111 ..... ----- ..... 0001001000 . @X_tb_rc
+FNEG 111111 ..... ----- ..... 0000101000 . @X_tb_rc
+FABS 111111 ..... ----- ..... 0100001000 . @X_tb_rc
+FNABS 111111 ..... ----- ..... 0010001000 . @X_tb_rc
+
### Floating-Point Arithmetic Instructions
FADD 111111 ..... ..... ..... ----- 10101 . @A_tab
diff --git a/target/ppc/translate/fp-impl.c.inc
b/target/ppc/translate/fp-impl.c.inc
index 4e18d350c0..2843f71122 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -280,82 +280,44 @@ TRANS(FCMPU, do_helper_cmp, gen_helper_FCMPU);
TRANS(FCMPO, do_helper_cmp, gen_helper_FCMPO);
/*** Floating-point move ***/
-/* fabs */
-/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
-static void gen_fabs(DisasContext *ctx)
-{
- TCGv_i64 t0;
- TCGv_i64 t1;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
- get_fpr(t0, rB(ctx->opcode));
- tcg_gen_andi_i64(t1, t0, ~(1ULL << 63));
- set_fpr(rD(ctx->opcode), t1);
- if (unlikely(Rc(ctx->opcode))) {
- gen_set_cr1_from_fpscr(ctx);
- }
-}
/* fmr - fmr. */
/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
-static void gen_fmr(DisasContext *ctx)
+static bool trans_FMR(DisasContext *ctx, arg_FMR *a)
{
TCGv_i64 t0;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
+ REQUIRE_INSNS_FLAGS(ctx, FLOAT);
+ REQUIRE_FPU(ctx);
t0 = tcg_temp_new_i64();
- get_fpr(t0, rB(ctx->opcode));
- set_fpr(rD(ctx->opcode), t0);
- if (unlikely(Rc(ctx->opcode))) {
+ get_fpr(t0, a->rb);
+ set_fpr(a->rt, t0);
+ if (unlikely(a->rc)) {
gen_set_cr1_from_fpscr(ctx);
}
+ return true;
}
-/* fnabs */
-/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
-static void gen_fnabs(DisasContext *ctx)
+/* XXX: beware that f{neg, abs, nabs} never checks for NaNs nor update FPSCR */
+static bool do_move_b(DisasContext *ctx, arg_X_tb_rc *a, int64_t val,
+ void (*tcg_op)(TCGv_i64, TCGv_i64, int64_t))
{
- TCGv_i64 t0;
- TCGv_i64 t1;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
+ TCGv_i64 t0, t1;
+ REQUIRE_INSNS_FLAGS(ctx, FLOAT);
+ REQUIRE_FPU(ctx);
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
- get_fpr(t0, rB(ctx->opcode));
- tcg_gen_ori_i64(t1, t0, 1ULL << 63);
- set_fpr(rD(ctx->opcode), t1);
- if (unlikely(Rc(ctx->opcode))) {
+ get_fpr(t0, a->rb);
+ tcg_op(t1, t0, val);
+ set_fpr(a->rt, t1);
+ if (unlikely(a->rc)) {
gen_set_cr1_from_fpscr(ctx);
}
+ return true;
}
-/* fneg */
-/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
-static void gen_fneg(DisasContext *ctx)
-{
- TCGv_i64 t0;
- TCGv_i64 t1;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
- get_fpr(t0, rB(ctx->opcode));
- tcg_gen_xori_i64(t1, t0, 1ULL << 63);
- set_fpr(rD(ctx->opcode), t1);
- if (unlikely(Rc(ctx->opcode))) {
- gen_set_cr1_from_fpscr(ctx);
- }
-}
+TRANS(FNEG, do_move_b, 1ULL << 63, tcg_gen_xori_i64);
+TRANS(FABS, do_move_b, ~(1ULL << 63), tcg_gen_andi_i64);
+TRANS(FNABS, do_move_b, 1ULL << 63, tcg_gen_ori_i64);
/* fcpsgn: PowerPC 2.05 specification */
/* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
diff --git a/target/ppc/translate/fp-ops.c.inc
b/target/ppc/translate/fp-ops.c.inc
index 502453da35..5053cb135c 100644
--- a/target/ppc/translate/fp-ops.c.inc
+++ b/target/ppc/translate/fp-ops.c.inc
@@ -10,10 +10,6 @@ GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
GEN_HANDLER_E(stfdepx, 0x1F, 0x1F, 0x16, 0x00000001, PPC_NONE, PPC2_BOOKE206),
GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
-GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
-GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
-GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
-GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
--
2.49.0
