Re: [PATCH v2 091/101] target/arm: Implement SME2 counted predicate register load/store

[Peter Maydell]

On Sun, 22 Jun 2025 at 01:00, Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> Implement the SVE2p1 consecutive register LD1/ST1,
> and the SME2 strided register LD1/ST1.
>



> +static bool gen_ldst_zcrr_c(DisasContext *s, arg_zcrr_ldst *a,
> +                            bool is_write, bool strided)
> +{
> +    TCGv_i64 addr = tcg_temp_new_i64();
> +
> +    tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->esz);
> +    tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
> +    return gen_ldst_c(s, addr, a->rd, a->png, a->esz, is_write,
> +                      a->nreg, strided);
> +}
> +
> +static bool gen_ldst_zcri_c(DisasContext *s, arg_zcri_ldst *a,
> +                            bool is_write, bool strided)
> +{
> +    TCGv_i64 addr = tcg_temp_new_i64();
> +
> +    tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn),
> +                     a->imm * vec_full_reg_size(s));
> +    return gen_ldst_c(s, addr, a->rd, a->png, a->esz, is_write,
> +                      a->nreg, strided);
> +}
> +
> +TRANS_FEAT(LD1_zcrr, aa64_sme2_or_sve2p1, gen_ldst_zcrr_c, a, false, false)
> +TRANS_FEAT(LD1_zcri, aa64_sme2_or_sve2p1, gen_ldst_zcri_c, a, false, false)
> +TRANS_FEAT(ST1_zcrr, aa64_sme2_or_sve2p1, gen_ldst_zcrr_c, a, true, false)
> +TRANS_FEAT(ST1_zcri, aa64_sme2_or_sve2p1, gen_ldst_zcri_c, a, true, false)
> +
> +TRANS_FEAT(LD1_zcrr_stride, aa64_sme2, gen_ldst_zcrr_c, a, false, true)
> +TRANS_FEAT(LD1_zcri_stride, aa64_sme2, gen_ldst_zcri_c, a, false, true)
> +TRANS_FEAT(ST1_zcrr_stride, aa64_sme2, gen_ldst_zcrr_c, a, true, true)
> +TRANS_FEAT(ST1_zcri_stride, aa64_sme2, gen_ldst_zcri_c, a, true, true)

These seem to be missing the

  if IsFeatureImplemented(FEAT_SVE2p1) then CheckSVEEnabled(); else
CheckStreamingSVEEnabled();

SVE-enabled checks that the pseudocode has?

thanks
-- PMM