On 2025/6/27 上午11:01, Song Gao wrote:
ntroduce the advanced extended interrupt controllers (AVECINTC). This
feature will allow each core to have 256 independent interrupt vectors
and MSI interrupts can be independently routed to any vector on any CPU.
The whole topology of irqchips in LoongArch machines looks like this if
AVECINTC is supported:
+-----+ +-----------------------+ +-------+
| IPI | --> | CPUINTC | <-- | Timer |
+-----+ +-----------------------+ +-------+
^ ^ ^
| | |
+---------+ +----------+ +---------+ +-------+
| EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |
+---------+ +----------+ +---------+ +-------+
^ ^
| |
+---------+ +---------+
| PCH-PIC | | PCH-MSI |
+---------+ +---------+
I think this topology has a little problem, PCH-MSI is connected to
EIOINTC always, AVECINTC is fully new MSI interrupt controller. AVECINTC
can coexist with PCH-MSI conroller.
MSI interrupt of device can connect to PCH-MSI or AVECINTC, it depends
on how MSI vector is allocated on VM.
Regards
Bibo Mao
^ ^ ^
| | |
+---------+ +---------+ +---------+
| Devices | | PCH-LPC | | Devices |
+---------+ +---------+ +---------+
^
|
+---------+
| Devices |
+---------+
We can see more about AVECINTC on linux driver code[1]
and loongarch msg interrupts on volI 6.2 Message-Interrupts
Tested the code using the virion-net NIC the start scripts is kernel.sh at[3]
and then
run 'ifconfig eth0 192.168.122.12'
[1]:
https://github.com/torvalds/linux/blob/master/drivers/irqchip/irq-loongarch-avec.c
[2]:
https://github.com/loongson/LoongArch-Documentation/releases/download/2023.04.20/LoongArch-Vol1-v1.10-EN.pdf
[3]:
https://github.com/gaosong715/qemu/releases/download/pull-loongarch-20250514/kernel.sh
v3:
1: Implement the read-clear feature for CSR_MSGIR register
2: Fix some code style;
3: Merge patch8 and patch9 into one patch8;
4: Fix patch7 get wrong cpu_num and irq_num;
5: Add vmstate_msg for messag-interrupt registers migrate;
6: Update test scripts use '-bios', because kernel use avec need acpi
support. the bios is qemu/pc_bios/edk2-loongarch64-code.fd.bz2.
v2:
1: Use one irqline for avec parent_irq;
2; Correct avec memroy area;
3; Pch-msi not connecet to avec when avec is enabled and drop patch 7;
4: Add misc_feature and misc_status for misc features an misc
Thanks.
Song Gao
Song Gao (9):
hw/loongarch: move some machine define to virt.h
hw/loongarch: add virt feature avecintc support
loongarch: add a advance interrupt controller device
target/loongarch: add msg interrupt CSR registers
hw/loongarch: AVEC controller add a MemoryRegion
hw/loongarch: Implement avec controller imput and output pins
hw/loongarch: Implement avec set irq
target/loongarch: CPU enable msg interrupts.
target/loongarch:Implement csrrd CSR_MSGIR register
hw/intc/Kconfig | 3 +
hw/intc/loongarch_avec.c | 153 ++++++++++++++++++
hw/intc/meson.build | 1 +
hw/loongarch/Kconfig | 1 +
hw/loongarch/virt.c | 89 +++++++++-
include/hw/intc/loongarch_avec.h | 36 +++++
include/hw/loongarch/virt.h | 36 +++++
include/hw/pci-host/ls7a.h | 2 +
target/loongarch/cpu-csr.h | 9 +-
target/loongarch/cpu.c | 17 ++
target/loongarch/cpu.h | 34 ++--
target/loongarch/csr.c | 5 +
target/loongarch/machine.c | 25 ++-
target/loongarch/tcg/csr_helper.c | 21 +++
target/loongarch/tcg/helper.h | 1 +
.../tcg/insn_trans/trans_privileged.c.inc | 1 +
16 files changed, 405 insertions(+), 29 deletions(-)
create mode 100644 hw/intc/loongarch_avec.c
create mode 100644 include/hw/intc/loongarch_avec.h
