> > +/*
> > + * Only used for the CPU models with CPUID level < 4.
> > + * These CPUs (CPUID level < 4) only use CPUID leaf 2 to present
> > + * cache information.
> > + *
> > + * Note: This cache model is just a default one, and is not
> > + * guaranteed to match real hardwares.
> > + */
> > +static const CPUCaches legacy_intel_cpuid2_cache_info = {
> > + .l1d_cache = &(CPUCacheInfo) {
> > + .type = DATA_CACHE,
> > + .level = 1,
> > + .size = 32 * KiB,
> > + .self_init = 1,
> > + .line_size = 64,
> > + .associativity = 8,
> > + .sets = 64,
> > + .partitions = 1,
> > + .no_invd_sharing = true,
> > + .share_level = CPU_TOPOLOGY_LEVEL_CORE,
> > + },
> > + .l1i_cache = &(CPUCacheInfo) {
> > + .type = INSTRUCTION_CACHE,
> > + .level = 1,
> > + .size = 32 * KiB,
> > + .self_init = 1,
> > + .line_size = 64,
> > + .associativity = 8,
> > + .sets = 64,
> > + .partitions = 1,
> > + .no_invd_sharing = true,
> > + .share_level = CPU_TOPOLOGY_LEVEL_CORE,
> > + },
> > + .l2_cache = &(CPUCacheInfo) {
> > + .type = UNIFIED_CACHE,
> > + .level = 2,
> > + .size = 2 * MiB,
> > + .self_init = 1,
> > + .line_size = 64,
> > + .associativity = 8,
> > + .sets = 4096,
> > + .partitions = 1,
> > + .no_invd_sharing = true,
> > + .share_level = CPU_TOPOLOGY_LEVEL_CORE,
> > + },
> > + .l3_cache = &(CPUCacheInfo) {
> > + .type = UNIFIED_CACHE,
> > + .level = 3,
> > + .size = 16 * MiB,
> > + .line_size = 64,
> > + .associativity = 16,
> > + .sets = 16384,
> > + .partitions = 1,
> > + .lines_per_tag = 1,
> > + .self_init = true,
> > + .inclusive = true,
> > + .complex_indexing = true,
> > + .share_level = CPU_TOPOLOGY_LEVEL_DIE,
> > + },
>
> Does this cache information match the real legacy HW or just an emulation
> of Qemu?
This is the pure emulation and it doesn't macth any HW :-(, and is a
"hybrid" result of continuously modifying and adding new cache features
(like the virtual L3). But for compatibility reasons, I abstracte it
into this special cache model, used only for older CPUs.
This way, at least modern CPUs won't be burdened by old historical
issues.
Thanks,
Zhao
