On 7/4/25 4:19 PM, Cornelia Huck wrote:
> While a trailing comma is not broken for SET_IDREG invocations, it
> does look odd; use a semicolon instead.
>
> Fixes: f1fd81291c91 ("arm/cpu: Store aa64mmfr0-3 into the idregs array")
> Fixes: def3f1c1026a ("arm/cpu: Store aa64dfr0/1 into the idregs array")
> Signed-off-by: Cornelia Huck <coh...@redhat.com>
Reviewed-by: Eric Auger <eric.au...@redhat.com>
Eric
> ---
> target/arm/tcg/cpu64.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
> index 00e12ed44ae8..d2f743fb3913 100644
> --- a/target/arm/tcg/cpu64.c
> +++ b/target/arm/tcg/cpu64.c
> @@ -352,7 +352,7 @@ static void aarch64_a76_initfn(Object *obj)
> cpu->clidr = 0x82000023;
> cpu->ctr = 0x8444C004;
> cpu->dcz_blocksize = 4;
> - SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408ull),
> + SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408ull);
> SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull);
> SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull);
> SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101122ull);
> @@ -426,8 +426,8 @@ static void aarch64_a64fx_initfn(Object *obj)
> cpu->reset_sctlr = 0x30000180;
> SET_IDREG(isar, ID_AA64PFR0, 0x0000000101111111); /* No RAS Extensions */
> SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000000);
> - SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408),
> - SET_IDREG(isar, ID_AA64DFR1, 0x0000000000000000),
> + SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408);
> + SET_IDREG(isar, ID_AA64DFR1, 0x0000000000000000);
> SET_IDREG(isar, ID_AA64AFR0, 0x0000000000000000);
> SET_IDREG(isar, ID_AA64AFR1, 0x0000000000000000);
> SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000001122);
> @@ -678,13 +678,13 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
> cpu->dcz_blocksize = 4;
> SET_IDREG(isar, ID_AA64AFR0, 0x00000000);
> SET_IDREG(isar, ID_AA64AFR1, 0x00000000);
> - SET_IDREG(isar, ID_AA64DFR0, 0x000001f210305519ull),
> - SET_IDREG(isar, ID_AA64DFR1, 0x00000000),
> + SET_IDREG(isar, ID_AA64DFR0, 0x000001f210305519ull);
> + SET_IDREG(isar, ID_AA64DFR1, 0x00000000);
> SET_IDREG(isar, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG */
> SET_IDREG(isar, ID_AA64ISAR1, 0x0011000001211032ull);
> SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull);
> - SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull),
> - SET_IDREG(isar, ID_AA64MMFR2, 0x0220011102101011ull),
> + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull);
> + SET_IDREG(isar, ID_AA64MMFR2, 0x0220011102101011ull);
> SET_IDREG(isar, ID_AA64PFR0, 0x1101110120111112ull); /* GIC filled in
> later */
> SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull);
> SET_IDREG(isar, ID_AFR0, 0x00000000);
