Since v4: - Moved MECID_WIDTH from cpu.h to internal.h - Fixed stray ';'s in access and write functions - Use of GET_IDREG/FIELD_DP64/SET_IDREG for setting feature in ID regs - Sorted correctly isar_feature_aa64_* AA64MMFR3 tests - Simplified/unified accessfn for cache instructions - Fixed how cache instruction-related registers are registered in the cpu
v1: https://mail.gnu.org/archive/html/qemu-devel/2025-06/msg04598.html v2: https://mail.gnu.org/archive/html/qemu-devel/2025-07/msg01799.html v3: https://mail.gnu.org/archive/html/qemu-devel/2025-07/msg02338.html v4: https://mail.gnu.org/archive/html/qemu-devel/2025-07/msg02488.html This series adds support for all FEAT_MEC registers and cache instructions to the Arm64 max CPU. It includes the FEAT_MEC registers and cache maintenance instructions, but does not modify the translation regimes to support the MECIDs, so no encryption is supported yet. However, software stacks that rely on FEAT_MEC should work properly at this point. I'm currently exploring possibilities to support FEAT_MEC encryption (or obfuscation, for testing purposes) in QEMU for the various translation regimes on arm64, hence the encryption part of FEAT_MEC will be contributed later and is not targeted for QEMU 10.1. Cheers, Gustavo Gustavo Romero (6): target/arm: Add the MECEn SCR_EL3 bit target/arm: Add FEAT_MEC registers target/arm: Add FEAT_SCTLR2 target/arm: Add FEAT_TCR2 target/arm: Implement FEAT_MEC cache instructions target/arm: Advertise FEAT_MEC in cpu max docs/system/arm/emulation.rst | 5 + target/arm/cpu-features.h | 15 +++ target/arm/cpu.h | 27 ++++ target/arm/helper.c | 232 ++++++++++++++++++++++++++++++++++ target/arm/internals.h | 23 ++++ target/arm/tcg/cpu64.c | 7 +- 6 files changed, 308 insertions(+), 1 deletion(-) -- 2.34.1
