Hi,
ntroduce the advanced extended interrupt controllers (AVECINTC). This
feature will allow each core to have 256 independent interrupt vectors
and MSI interrupts can be independently routed to any vector on any CPU.
The whole topology of irqchips in LoongArch machines looks like this if
AVECINTC is supported:
+-----+ +---------------------------------+ +-------+
| IPI | --> | CPUINTC | <-- | Timer |
+-----+ +---------------------------------+ +-------+
^ ^ ^
| | |
+-------------+ +----------+ +---------+ +-------+
| EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |
+-------------+ +----------+ +---------+ +-------+
^ ^ ^
| | |
+---------+ +---------+ |
| PCH-PIC | | PCH-MSI | |
+---------+ +---------+ |
^ ^ ^ |
| | | |
+---------+ +---------+ +---------+
| Devices | | PCH-LPC | | Devices |
+---------+ +---------+ +---------+
^
|
+---------+
| Devices |
+---------+
We can see more about AVECINTC on linux driver code[1]
and loongarch msg interrupts on volI 6.2 Message-Interrupts
Tested the code using the virion-net NIC the start scripts is kernel.sh at[3]
and then
run 'ifconfig eth0 192.168.122.12' or
test avec plug and unplug interfaces
1 run kernel.sh[3]
2 telnet localhost 4418;
3 run QOM 'device_add
la464-loongarch-cpu,socket-id=2,core-id=0,thread-id=0,id=cpu-2'
4 run vm 'ifconfig eth0 192.168.122.12';
5 run QOM 'device_de cpu-2'
6 run vm 'ifconfig eth0 192.168.122.11';
[1]:
https://github.com/torvalds/linux/blob/master/drivers/irqchip/irq-loongarch-avec.c
[2]:
https://github.com/loongson/LoongArch-Documentation/releases/download/2023.04.20/LoongArch-Vol1-v1.10-EN.pdf
[3]:
https://github.com/gaosong715/qemu/releases/download/pull-loongarch-20250514/kernel.sh
v5:
1: rebase and R_b;
2; change patch2 and patch3 commit message;
3, change virt_is_avecintc_enabled() to virt_has_avecintc();
4: remove set and clean CSR_ECFG.bit15;
5; patch11 add some check lvms->avec, beacuse someone my set avecintc=off.
v4:
1: Implemetnt the AVEC plug/unplug interface. test with devcice-add
cpu and device-add and then setup the virtio-net nic. new patch11;
2: add a new patch1 move some machine define to virt.h;
3; add a new patch3 to implemet write/raad misc' avec feature and
status bit.
4: Simplification of patch8 and patch10 as per bibo's suggestion.
v3:
1: Implement the read-clear feature for CSR_MSGIR register
2: Fix some code style;
3: Merge patch8 and patch9 into one patch8;
4: Fix patch7 get wrong cpu_num and irq_num;
5: Add vmstate_msg for messag-interrupt registers migrate;
6: Update test scripts use '-bios', because kernel use avec need acpi
support. the bios is qemu/pc_bios/edk2-loongarch64-code.fd.bz2.
Thanks.
Song Gao
Song Gao (11):
target/loongarch: move some machine dfine to virt.h
hw/loongarch: add virt feature avecintc support
hw/loongarch: add misc register supoort avecintc
loongarch: add a advance interrupt controller device
target/loongarch: add msg interrupt CSR registers
hw/loongarch: AVEC controller add a MemoryRegion
hw/loongarch: Implement avec controller imput and output pins
hw/loongarch: Implement avec set irq
target/loongarch: CPU enable msg interrupts.
target/loongarch:Implement csrrd CSR_MSGIR register
hw/loongarch: Implement AVEC plug/unplug interfaces
hw/intc/Kconfig | 3 +
hw/intc/loongarch_avec.c | 214 ++++++++++++++++++
hw/intc/meson.build | 1 +
hw/loongarch/Kconfig | 1 +
hw/loongarch/virt.c | 98 +++++++-
include/hw/intc/loongarch_avec.h | 36 +++
include/hw/loongarch/virt.h | 33 +++
include/hw/pci-host/ls7a.h | 2 +
target/loongarch/cpu-csr.h | 9 +-
target/loongarch/cpu.c | 10 +
target/loongarch/cpu.h | 34 +--
target/loongarch/csr.c | 5 +
target/loongarch/machine.c | 27 ++-
target/loongarch/tcg/csr_helper.c | 22 ++
target/loongarch/tcg/helper.h | 1 +
.../tcg/insn_trans/trans_privileged.c.inc | 1 +
16 files changed, 468 insertions(+), 29 deletions(-)
create mode 100644 hw/intc/loongarch_avec.c
create mode 100644 include/hw/intc/loongarch_avec.h
--
2.34.1
