Hi XieBo, Could you give the method on how to test it? Thanks, Zhiwei
获取Outlook for Android<https://aka.ms/AAb9ysg> ________________________________ From: qemu-devel-bounces+baxiantai=gmail....@nongnu.org <qemu-devel-bounces+baxiantai=gmail....@nongnu.org> on behalf of 谢波 <x...@ultrarisc.com> Sent: Friday, July 11, 2025 5:28:10 PM To: qemu-devel@nongnu.org <qemu-devel@nongnu.org> Cc: alistair.fran...@wdc.com <alistair.fran...@wdc.com>; pal...@dabbelt.com <pal...@dabbelt.com>; pbonz...@redhat.com <pbonz...@redhat.com>; a...@brainfault.org <a...@brainfault.org>; anup.pa...@wdc.com <anup.pa...@wdc.com> Subject: [PATCH for v10.0.0] target/riscv/kvm/kvm-cpu: Fixed the issue of resume after QEMU+KVM migration This is v3 of this patch to fix patch format This patch fixes two critical issues in QEMU with KVM: 1. Post-Migration Failure in User Mode: When QEMU with KVM is running in user mode, the guest may fail to function correctly after migration. 2. Multi-Core Guest Inconsistency: After migration, only the first CPU (core 0) remains functional, while all other cores become unresponsive. Changes include: - Properly restoring guest privileged state during register synchronization. - Correctly updating multi-core state after migration to ensure all cores are active. Signed-off-by: Xie Bo <x...@ultrarisc.com> --- target/riscv/kvm/kvm-cpu.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 75724b6af4..a15caa20ce 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -576,6 +576,14 @@ static int kvm_riscv_get_regs_core(CPUState *cs) } env->pc = reg; + /*Restore the guest's privileged level after migration*/ + ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, mode), ®); + if (ret) { + return ret; + } + if(reg != 3) { + env->priv = reg; + } for (i = 1; i < 32; i++) { uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); ret = kvm_get_one_reg(cs, id, ®); @@ -601,6 +609,15 @@ static int kvm_riscv_put_regs_core(CPUState *cs) return ret; } + /*Save guest privilege level before migration*/ + reg = env->priv; + if(reg != 3) { + ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, mode), ®); + if (ret) { + return ret; + } + } + for (i = 1; i < 32; i++) { uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); reg = env->gpr[i]; @@ -1289,6 +1306,12 @@ int kvm_arch_put_registers(CPUState *cs, int level, Error **errp) return ret; } + /*Ensure all non-core 0 CPUs are runnable after migration*/ + if((level == KVM_PUT_FULL_STATE) && (cs->cpu_index != 0)){ + RISCVCPU *cpu = RISCV_CPU(cs); + ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); + } + if (KVM_PUT_RESET_STATE == level) { RISCVCPU *cpu = RISCV_CPU(cs); if (cs->cpu_index == 0) { -- 2.34.1 > -----原始邮件----- > 发件人: 谢波 <x...@ultrarisc.com> > 发送时间:2025-05-26 15:45:52 (星期一) > 收件人: qemu-devel@nongnu.org > 抄送: alistair.fran...@wdc.com, pal...@dabbelt.com, pbonz...@redhat.com, > a...@brainfault.org, anup.pa...@wdc.com > 主题: Re: [PATCH V2] target/riscv/kvm/kvm-cpu: Fixed the issue of resume after > QEMU+KVM migration > > This is v2 of this patch with no functional changes; adding CC. > > --- > target/riscv/kvm/kvm-cpu.c | 23 +++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > --- a/target/riscv/kvm/kvm-cpu.c > +++ b/target/riscv/kvm/kvm-cpu.c > @@ -576,6 +576,14 @@ static int kvm_riscv_get_regs_core(CPUState *cs) > } > env->pc = reg; > > + /* Restore guest privilege level after migration */ > + ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, mode), ®); > + if (ret) { > + return ret; > + } > + if (reg != 3) { > + env->priv = reg; > + } > > for (i = 1; i < 32; i++) { > uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); > ret = kvm_get_one_reg(cs, id, ®); > @@ -601,6 +609,15 @@ static int kvm_riscv_put_regs_core(CPUState *cs) > return ret; > } > > + /* Save guest privilege level before migration */ > + reg = env->priv; > + if (reg != 3) { > + ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, mode), ®); > + if (ret) { > + return ret; > + } > + } > + > for (i = 1; i < 32; i++) { > uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); > reg = env->gpr[i]; > @@ -1289,6 +1306,12 @@ int kvm_arch_put_registers(CPUState *cs, int level, > Error **errp) > return ret; > } > > + /* Ensure all non-core 0 CPUs are runnable after migration */ > + if ((level == KVM_PUT_FULL_STATE) && (cs->cpu_index != 0)) { > + RISCVCPU *cpu = RISCV_CPU(cs); > + ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); > + if (ret) { > + return ret; > + } > + } > > if (KVM_PUT_RESET_STATE == level) { > RISCVCPU *cpu = RISCV_CPU(cs); > if (cs->cpu_index == 0) { > -- > 2.34.1 > > > > > > -----原始邮件----- > > 发件人: 谢波 <x...@ultrarisc.com> > > 发送时间:2025-05-19 17:41:36 (星期一) > > 收件人: qemu-devel@nongnu.org > > 抄送: alistair.fran...@wdc.com, pal...@dabbelt.com, pbonz...@redhat.com > > 主题: [PATCH] target/riscv/kvm/kvm-cpu: Fixed the issue of resume after > > QEMU+KVM migration > > > > This patch fixes two critical issues in QEMU with KVM: > > > > 1. Post-Migration Failure in User Mode: When QEMU with KVM is running in > > user mode, the guest may fail to function correctly after migration due to > > incorrect privilege state restoration. > > > > 2. Multi-Core Guest Inconsistency: After migration, only the first CPU > > (core 0) remains functional, while all other cores become unresponsive. > > This patch ensures all cores are properly set to runnable state after > > migration. > > > > Changes include: > > - Properly restoring guest privileged state during register synchronization. > > - Correctly updating multi-core state after migration to ensure all cores > > are active. > > > > Signed-off-by: Xie Bo <x...@ultrarisc.com> > > > > --- > > target/riscv/kvm/kvm-cpu.c | 23 +++++++++++++++++++++++ > > 1 file changed, 23 insertions(+) > > > > --- a/target/riscv/kvm/kvm-cpu.c > > +++ b/target/riscv/kvm/kvm-cpu.c > > @@ -576,6 +576,14 @@ static int kvm_riscv_get_regs_core(CPUState *cs) > > } > > env->pc = reg; > > > > + /* Restore guest privilege level after migration */ > > + ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, mode), ®); > > + if (ret) { > > + return ret; > > + } > > + if (reg != 3) { > > + env->priv = reg; > > + } > > > > for (i = 1; i < 32; i++) { > > uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); > > ret = kvm_get_one_reg(cs, id, ®); > > @@ -601,6 +609,15 @@ static int kvm_riscv_put_regs_core(CPUState *cs) > > return ret; > > } > > > > + /* Save guest privilege level before migration */ > > + reg = env->priv; > > + if (reg != 3) { > > + ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, mode), ®); > > + if (ret) { > > + return ret; > > + } > > + } > > + > > for (i = 1; i < 32; i++) { > > uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); > > reg = env->gpr[i]; > > @@ -1289,6 +1306,12 @@ int kvm_arch_put_registers(CPUState *cs, int level, > > Error **errp) > > return ret; > > } > > > > + /* Ensure all non-core 0 CPUs are runnable after migration */ > > + if ((level == KVM_PUT_FULL_STATE) && (cs->cpu_index != 0)) { > > + RISCVCPU *cpu = RISCV_CPU(cs); > > + ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); > > + if (ret) { > > + return ret; > > + } > > + } > > > > if (KVM_PUT_RESET_STATE == level) { > > RISCVCPU *cpu = RISCV_CPU(cs); > > if (cs->cpu_index == 0) { > > -- > > 2.34.1 > > > > ______________________www.ultrarisc.com > > 重要提示：本邮件包括附件的内容是受法律保护的保密信息，如果您不是指定收件人，请立即将本邮件删除，法律禁止任何非法的披露、复制、传播或以任何方式使用本邮件。本邮件中包含的意见、建议是基于或受到我方表达和定义的条款及条件的限定，如无我方的正式书面澄清或授权，不可被单独作为任何情形下的证据或依据。感谢您的理解与配合。版权所有。IMPORTANT > > NOTICE: This email, including its attachment if any, is confidential. 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Any opinions and suggestions contained in this email are subject to the terms and conditions expressed and defined by us and should not be relied upon unconditionally under any circumstances unless they are confirmed in official written clarification or authorization from us. Thank you for your understanding and cooperation.All rights reserved.
