On 7/13/25 9:27 AM, Richard Henderson wrote:
On 7/11/25 23:02, Richard Henderson wrote:
On 7/11/25 08:08, Gustavo Romero wrote:
Add FEAT_SCTLR2, which introduces the SCTLR2_EL1, SCTLR2_EL2, and
SCTLR2_EL3 registers. These registers are extensions of the SCTLR_ELx
ones.
Because the bits in these registers depend on other CPU features, and
only FEAT_MEC is supported at the moment, this commit only implements
the EMEC bits in CTLR2_EL2 and SCTLR2_EL3.
Signed-off-by: Gustavo Romero <gustavo.rom...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu-features.h | 5 +++
target/arm/cpu.c | 3 ++
target/arm/cpu.h | 15 +++++++
target/arm/helper.c | 80 +++++++++++++++++++++++++++++++++++
target/arm/internals.h | 1 +
target/arm/tcg/cpu64.c | 5 ++-
7 files changed, 109 insertions(+), 1 deletion(-)
Bisect points to this patch as breaking
45/60 qemu:func-thorough+func-aarch64-thorough+thorough /
func-aarch64-aarch64_rme_sbsaref
TIMEOUT 1200.01s killed by signal 15 SIGTERM
46/60 qemu:func-thorough+func-aarch64-thorough+thorough /
func-aarch64-aarch64_rme_virt
TIMEOUT 1200.02s killed by signal 15 SIGTERM
Try make check-functional-aarch64.
This is caused by the realm os being new enough to try to access SCTLR2, but
the op-tee
firmware is not new enough to enable access to SCTLR2. So Realm EL2
unexpectedly but
correctly traps to EL3, and the whole stack gets wedged:
2025-07-13 10:16:12,680: SMC_RMI_REALM_ACTIVATE
2025-07-13 10:16:12,680: 10045c6c000 > RMI_SUCCESS
2025-07-13 10:16:12,689: Unexpected exception on CPU #0:
Pierrick, I believe you built the rme test images. Is there perhaps a newer
version of
the firmware that supports (at least) SCTLR2 and TCR2?
It seems that TF-A has an option 'ENABLE_FEAT_SCTLR2'.
I will try to build with it, and current series, and see how it goes.
r~
