Hi, To avoid the series being too trivial, I've merged the two previous series together again.
This series is based on: https://lore.kernel.org/qemu-devel/20250711102143.1622339-1-zhao1....@intel.com/ And you can find the codes at: https://gitlab.com/zhao.liu/qemu/-/tree/cache-model-v3.0-rebase-07-10-2025?ref_type=heads Part 1 (Patch 1-3) ================== Since the previsor unified cache model series has already introduced a new compat property "x-vendor-cpuid-only-v2", it's a chance to once again consolidate more vendor-specific CPUIDs. I also checked the CPUID leaves currently supported by Intel & AMD and found that since the previous "x-vendor-cpuid-only," AMD has already cleaned up the Intel-specific CPUIDs quite well. As for Intel, the only cleanup needed is for the "extended function CPUID" leaves (0x80000000~0x80000008). That's what these patches does. Considerring the disscussion around AMD's arch capabilities MSR, explicitly changing feature bits in QEMU that require host support is inappropriate. CPUID adjustments based on the vendor should be limited to parts that are fully emulated within QEMU (such as topology, vendor, etc.). Therefore, in v2, I dropped the modifications to 0x80000007 and narrowed the changes to 0x80000008 to only the fields related to CPU topology. Previous v1: https://lore.kernel.org/qemu-devel/20250627035129.2755537-1-zhao1....@intel.com/ Part 2 (Patch 4-7) ================== These patches collect and organize several topology-related cleanups and fixes. Comparing with v1, I provides the oveflow example for patch 6 & 7. Note, In addition to the 0x1, 0x4, and 0x8000001d leaves involved in the patch series, there is also the 0x1f leaf related to topology. However, the upper limit for CPUID.1FH.EBX[bits 15:0] is 65,535 threads, which provides enough room. Therefore, this field does not currently require overflow checks. PS: The previous patch 4 tried to fix overflow directly. But now we have the "x-vendor-cpuid-only-v2", it's a chance to fix addressable ID for new machines. Previous v1: https://lore.kernel.org/qemu-devel/20250227062523.124601-1-zhao1....@intel.com/ Thanks and Best Regards, Zhao --- Chuang Xu (1): i386/cpu: Fix number of addressable IDs field for CPUID.01H.EBX[23:16] Qian Wen (2): i386/cpu: Fix cpu number overflow in CPUID.01H.EBX[23:16] i386/cpu: Fix overflow of cache topology fields in CPUID.04H Zhao Liu (4): i386/cpu: Mark EBX/ECX/EDX in CPUID 0x80000000 leaf as reserved for Intel i386/cpu: Mark CPUID 0x80000008 ECX bits[0:7] & [12:15] as reserved for Intel/Zhaoxin i386/cpu: Reorder CPUID leaves in cpu_x86_cpuid() i386/cpu: Honor maximum value for CPUID.8000001DH.EAX[25:14] target/i386/cpu.c | 130 ++++++++++++++++++++++++++++++---------------- 1 file changed, 84 insertions(+), 46 deletions(-) -- 2.34.1
