On Mon, Jul 14, 2025 at 04:59:40PM +0100, Shameer Kolothum wrote: > From: Nicolin Chen <nicol...@nvidia.com> > > Not all fields in the SMMU IDR registers are meaningful for userspace. > Only the following fields can be used: > > - IDR0: ST_LEVEL, TERM_MODEL, STALL_MODEL, TTENDIAN, CD2L, ASID16, TTF > - IDR1: SIDSIZE, SSIDSIZE > - IDR3: BBML, RIL > - IDR5: VAX, GRAN64K, GRAN16K, GRAN4K > > Use the relevant fields from these to check whether the host and emulated > SMMUv3 features are sufficiently aligned to enable accelerated SMMUv3 > support. > > To retrieve this information from the host, at least one vfio-pci device > must be assigned with "arm-smmuv3,accel=on" usage. Add a check to enforce > this. > > Note: > > ATS, PASID, and PRI features are currently not supported. Only devices > that do not require or make use of these features are expected to work.
Can we support ATS/PASID at least? I need to double check intel's series, but I somehow recall that there is a PASID cap support in the VFIO level, so VM could actually report ATS/PASID caps? The invalidation part could forward ATC_INV command too, as kernel supports that. Thanks Nicolin
