>-----Original Message-----
>From: Shameer Kolothum <shameerali.kolothum.th...@huawei.com>
>Subject: [RFC PATCH v3 05/15] hw/arm/smmuv3-accel: Introduce smmuv3
>accel device
>
>Also setup specific PCIIOMMUOps for accel SMMUv3 as accel
>SMMUv3 will have different handling for those ops callbacks
>in subsequent patches.
>
>The "accel" property is not yet added, so users cannot set it at this
>point. It will be introduced in a subsequent patch once the necessary
>support is in place.
>
>Signed-off-by: Shameer Kolothum
><shameerali.kolothum.th...@huawei.com>
>---
> hw/arm/meson.build | 3 +-
> hw/arm/smmu-common.c | 6 +++-
> hw/arm/smmuv3-accel.c | 66
>++++++++++++++++++++++++++++++++++++
> hw/arm/smmuv3-accel.h | 19 +++++++++++
> include/hw/arm/smmu-common.h | 3 ++
> 5 files changed, 95 insertions(+), 2 deletions(-)
> create mode 100644 hw/arm/smmuv3-accel.c
> create mode 100644 hw/arm/smmuv3-accel.h
>
>diff --git a/hw/arm/meson.build b/hw/arm/meson.build
>index dc68391305..6126eb1b64 100644
>--- a/hw/arm/meson.build
>+++ b/hw/arm/meson.build
>@@ -61,7 +61,8 @@ arm_common_ss.add(when: 'CONFIG_ARMSSE', if_true:
>files('armsse.c'))
> arm_common_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c',
>'mcimx7d-sabre.c'))
> arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP', if_true:
>files('fsl-imx8mp.c'))
> arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP_EVK', if_true:
>files('imx8mp-evk.c'))
>-arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true:
>files('smmuv3.c'))
>+arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c'))
>+arm_ss.add(when: ['CONFIG_ARM_SMMUV3', 'CONFIG_IOMMUFD'], if_true:
>files('smmuv3-accel.c'))
> arm_common_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true:
>files('fsl-imx6ul.c', 'mcimx6ul-evk.c'))
> arm_common_ss.add(when: 'CONFIG_NRF51_SOC', if_true:
>files('nrf51_soc.c'))
> arm_ss.add(when: 'CONFIG_XEN', if_true: files(
>diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
>index 3a1080773a..6a58f574d3 100644
>--- a/hw/arm/smmu-common.c
>+++ b/hw/arm/smmu-common.c
>@@ -938,7 +938,11 @@ static const PCIIOMMUOps
>*smmu_iommu_ops_by_type(SMMUState *s)
> {
> SMMUBaseClass *sbc;
>
>- sbc = ARM_SMMU_CLASS(object_class_by_name(TYPE_ARM_SMMU));
>+ if (s->accel) {
>+ sbc =
>ARM_SMMU_CLASS(object_class_by_name(TYPE_ARM_SMMUV3_ACCEL));
>+ } else {
>+ sbc =
>ARM_SMMU_CLASS(object_class_by_name(TYPE_ARM_SMMU));
>+ }
> assert(sbc->iommu_ops);
>
> return sbc->iommu_ops;
>diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
>new file mode 100644
>index 0000000000..2eac9c6ff4
>--- /dev/null
>+++ b/hw/arm/smmuv3-accel.c
>@@ -0,0 +1,66 @@
>+/*
>+ * Copyright (c) 2025 Huawei Technologies R & D (UK) Ltd
>+ * Copyright (C) 2025 NVIDIA
>+ * Written by Nicolin Chen, Shameer Kolothum
>+ *
>+ * SPDX-License-Identifier: GPL-2.0-or-later
>+ */
>+
>+#include "qemu/osdep.h"
>+
>+#include "hw/arm/smmuv3.h"
>+#include "smmuv3-accel.h"
>+
>+static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *bs,
>SMMUPciBus *sbus,
>+ PCIBus *bus, int
>devfn)
>+{
>+ SMMUDevice *sdev = sbus->pbdev[devfn];
>+ SMMUv3AccelDevice *accel_dev;
>+
>+ if (sdev) {
>+ accel_dev = container_of(sdev, SMMUv3AccelDevice, sdev);
>+ } else {
>+ accel_dev = g_new0(SMMUv3AccelDevice, 1);
>+ sdev = &accel_dev->sdev;
>+
>+ sbus->pbdev[devfn] = sdev;
>+ smmu_init_sdev(bs, sdev, bus, devfn);
>+ }
>+
>+ return accel_dev;
>+}
>+
>+static AddressSpace *smmuv3_accel_find_add_as(PCIBus *bus, void
>*opaque,
>+ int devfn)
>+{
>+ SMMUState *bs = opaque;
>+ SMMUPciBus *sbus;
>+ SMMUv3AccelDevice *accel_dev;
>+ SMMUDevice *sdev;
>+
>+ sbus = smmu_get_sbus(bs, bus);
>+ accel_dev = smmuv3_accel_get_dev(bs, sbus, bus, devfn);
>+ sdev = &accel_dev->sdev;
>+
>+ return &sdev->as;
>+}
>+
>+static const PCIIOMMUOps smmuv3_accel_ops = {
>+ .get_address_space = smmuv3_accel_find_add_as,
>+};
>+
>+static void smmuv3_accel_class_init(ObjectClass *oc, const void *data)
>+{
>+ SMMUBaseClass *sbc = ARM_SMMU_CLASS(oc);
>+
>+ sbc->iommu_ops = &smmuv3_accel_ops;
>+}
>+
>+static const TypeInfo types[] = {
>+ {
>+ .name = TYPE_ARM_SMMUV3_ACCEL,
>+ .parent = TYPE_ARM_SMMUV3,
>+ .class_init = smmuv3_accel_class_init,
>+ }
In cover-letter, I see "-device arm-smmuv3", so where is above accel device
created so we could use smmuv3_accel_ops?
