在2024年5月6日周一 下午4:31，Jiaxun Yang写道：
> Hi all,
>
> This series implemented propper multiple core support for MIPS
> CPS systsm.
Ping :-)
This is a really long outstanding series, I just want to get some
review before respin.
Thanks
Jiaxun
>
> Previously all CPUs are being implemented as a smt thread in a
> single core. Now it respects topology supplied in QEMU args.
>
> To test:
> Build a latest kernel with 64r6el_defconfig (tested on 6.6,
> next-20240506).
>
> Then run:
> ```
> qemu-system-mips64el -M boston -cpu I6500 -kernel ~/linux-next/vmlinux
> -smp 4,cores=2,threads=2 -append "console=ttyS0,115200" -nographic
> ```
> In dmesg of guest kernel:
> ```
> [ 0.000000] VP topology {2,2} total 4
> ...
> [ 0.085190] smp: Bringing up secondary CPUs ...
> [ 0.090219] Primary instruction cache 64kB, VIPT, 4-way, linesize 64
> bytes.
> [ 0.095461] Primary data cache 64kB, 4-way, PIPT, no aliases,
> linesize 64 bytes
> [ 0.096658] CPU1 revision is: 0001b000 (MIPS I6500)
> [ 0.096718] FPU revision is: 20f30300
> [ 0.124711] Synchronize counters for CPU 1: done.
> [ 0.940979] Primary instruction cache 64kB, VIPT, 4-way, linesize 64
> bytes.
> [ 0.941041] Primary data cache 64kB, 4-way, PIPT, no aliases,
> linesize 64 bytes
> [ 0.941256] CPU2 revision is: 0001b000 (MIPS I6500)
> [ 0.941289] FPU revision is: 20f30300
> [ 0.965322] Synchronize counters for CPU 2: done.
> [ 1.260937] Primary instruction cache 64kB, VIPT, 4-way, linesize 64
> bytes.
> [ 1.261001] Primary data cache 64kB, 4-way, PIPT, no aliases,
> linesize 64 bytes
> [ 1.261172] CPU3 revision is: 0001b000 (MIPS I6500)
> [ 1.261209] FPU revision is: 20f30300
> [ 1.285390] Synchronize counters for CPU 3: done.
> [ 1.346985] smp: Brought up 1 node, 4 CPUs
> ```
>
> Please review.
>
> Thanks
>
> To: qemu-devel@nongnu.org
> Cc: Philippe Mathieu-Daudé <phi...@linaro.org>
>
> Signed-off-by: Jiaxun Yang <jiaxun.y...@flygoat.com>
> ---
> Jiaxun Yang (5):
> target/mips: Make globalnumber a CPU property
> hw/msic/mips_cmgcr: Implement multicore functions
> hw/msic/mips_cpc: Implement multi core support
> hw/mips/cps: Implement multi core support
> hw/mips/boston: Implement multi core support
>
> hw/mips/boston.c | 37 +++++++++-
> hw/mips/cps.c | 66 ++++++++++-------
> hw/misc/mips_cmgcr.c | 168
> +++++++++++++++++++++++++++++++++++--------
> hw/misc/mips_cpc.c | 97 ++++++++++++++++++-------
> include/hw/mips/cps.h | 1 +
> include/hw/misc/mips_cmgcr.h | 87 +++++++++++++++++++---
> include/hw/misc/mips_cpc.h | 15 +++-
> target/mips/cpu.c | 16 ++++-
> target/mips/cpu.h | 10 ++-
> target/mips/sysemu/machine.c | 5 +-
> 10 files changed, 403 insertions(+), 99 deletions(-)
> ---
> base-commit: 248f6f62df073a3b4158fd0093863ab885feabb5
> change-id: 20240506-mips-smp-9af9e71ad8c2
>
> Best regards,
> --
> Jiaxun Yang <jiaxun.y...@flygoat.com>
--
- Jiaxun
