Hi; here is a target-arm pullreq for rc0. It has various bugfixes; the biggest bit here is adding a handful of bfloat16 instructions we accidentally forgot to implement in the recent SVE2p1 feature. I consider those to count under the "bugfix" heading because without them we would UNDEF when we should not; plus this is still very early in the release cycle.
thanks -- PMM The following changes since commit e82989544e38062beeeaad88c175afbeed0400f8: Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2025-07-18 14:10:02 -0400) are available in the Git repository at: https://gitlab.com/pm215/qemu.git tags/pull-target-arm-20250721 for you to fetch changes up to 7724ca9a772594b96939ff549c74f46e11d7870b: accel/hvf: Display executable bit as 'X' (2025-07-21 13:38:33 +0100) ---------------------------------------------------------------- target-arm queue: * hvf: arm: Remove $pc from trace_hvf_data_abort() * target/arm: Correct encoding of Debug Communications Channel registers * hw/misc/ivshmem-pci: Improve error handling * target/arm: Provide always-false kvm_arm_*_supported() stubs for usermode * host-utils: Drop workaround for buggy Apple Clang __builtin_subcll() * hw/misc/max78000_aes: Comment Internal Key Storage * docs: Fix Aspeed title * Implement a handful of missing FEAT_SVE_B16_B16 insns * Fix bugs in FMAXQV, FMINQV, etc * Fix assert in LD1Q decode * hvf: arm: Add permission check in GIC sysreg handlers * hvf: arm: Emulate ICC_RPR_EL1 accesses properly * accel/hvf: Display executable bit as 'X' ---------------------------------------------------------------- Cédric Le Goater (1): docs: Fix Aspeed title Jackson Donaldson (1): hw/misc/max78000_aes: Comment Internal Key Storage Peter Maydell (14): target/arm: Correct encoding of Debug Communications Channel registers hw/misc/ivshmem-pci: Improve error handling target/arm: Provide always-false kvm_arm_*_supported() stubs for usermode host-utils: Drop workaround for buggy Apple Clang __builtin_subcll() target/arm: Add BFADD, BFSUB, BFMUL (unpredicated) target/arm: Add BFADD, BFSUB, BFMUL, BFMAXNM, BFMINNM (predicated) target/arm: Add BFMIN, BFMAX (predicated) target/arm: Add BFMUL (indexed) target/arm: Add BFMLA, BFMLS (vectors) target/arm: Add BFMLA, BFMLS (indexed) target/arm: Correct sense of FPCR.AH test for FMAXQV and FMINQV target/arm: Don't nest H() macro calls in SVE DO_REDUCE target/arm: Honour FPCR.AH=1 default NaN value in FMAXNMQV, FMINNMQV target/arm: Make LD1Q decode and trans fn agree about a->u Philippe Mathieu-Daudé (1): accel/hvf: Display executable bit as 'X' Zenghui Yu (3): hvf: arm: Remove $pc from trace_hvf_data_abort() hvf: arm: Add permission check in GIC sysreg handlers hvf: arm: Emulate ICC_RPR_EL1 accesses properly docs/system/arm/aspeed.rst | 1 + include/qemu/compiler.h | 13 ----- include/qemu/host-utils.h | 2 +- target/arm/kvm_arm.h | 35 +++++++++++++ target/arm/tcg/helper-sve.h | 32 ++++++++++++ target/arm/tcg/helper.h | 5 ++ target/arm/tcg/sve.decode | 5 +- accel/hvf/hvf-all.c | 2 +- hw/misc/ivshmem-pci.c | 9 +++- hw/misc/max78000_aes.c | 6 +++ target/arm/debug_helper.c | 13 ++++- target/arm/hvf/hvf.c | 10 +++- target/arm/tcg/sve_helper.c | 109 ++++++++++++++++++++++++++++++++++++----- target/arm/tcg/translate-sve.c | 97 ++++++++++++++++++++++++++---------- target/arm/tcg/vec_helper.c | 4 ++ target/arm/hvf/trace-events | 2 +- 16 files changed, 285 insertions(+), 60 deletions(-)
