From: Nicholas Piggin <npig...@gmail.com> If CPPR is lowered to preclude the pending interrupt, NSR should be cleared and the qemu_irq should be lowered. This avoids some cases of supurious interrupts.
Signed-off-by: Nicholas Piggin <npig...@gmail.com> Reviewed-by: Glenn Miles <mil...@linux.ibm.com> Reviewed-by: Michael Kowal <ko...@linux.ibm.com> Reviewed-by: Caleb Schlossin <cal...@linux.ibm.com> Tested-by: Gautam Menghani <gau...@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-14-npig...@gmail.com Signed-off-by: Cédric Le Goater <c...@redhat.com> --- hw/intc/xive.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index bc829bebe9d0..a0a60a24f510 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -110,6 +110,9 @@ void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring, uint8_t group_level) regs[TM_IPB], alt_regs[TM_PIPR], alt_regs[TM_CPPR], alt_regs[TM_NSR]); qemu_irq_raise(xive_tctx_output(tctx, ring)); + } else { + alt_regs[TM_NSR] = 0; + qemu_irq_lower(xive_tctx_output(tctx, ring)); } } -- 2.50.1
