Re: [PATCH v2] intc/riscv_aplic: Fix target register read when source is inactive

[Daniel Henrique Barboza]

On 7/28/25 2:51 AM, Yang Jialong wrote:

The RISC-V Advanced interrupt Architecture:
4.5.16. Interrupt targets:
If interrupt source i is inactive in this domain, register target[i] is
read-only zero.

Signed-off-by: Yang Jialong <z_baj...@yeah.net>
---

Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>

  hw/intc/riscv_aplic.c | 6 +++++-
  1 file changed, 5 insertions(+), 1 deletion(-)

v1 --> v2:
- Use '&' replace the error '*'.

diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index 4fa5f7597b..a1d9fa5085 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -628,7 +628,7 @@ static void riscv_aplic_request(void *opaque, int irq, int 
level)

static uint64_t riscv_aplic_read(void *opaque, hwaddr addr, unsigned size)

  {
-    uint32_t irq, word, idc;
+    uint32_t irq, word, idc, sm;
      RISCVAPLICState *aplic = opaque;

/* Reads must be 4 byte words */

@@ -696,6 +696,10 @@ static uint64_t riscv_aplic_read(void *opaque, hwaddr 
addr, unsigned size)
      } else if ((APLIC_TARGET_BASE <= addr) &&
              (addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) {
          irq = ((addr - APLIC_TARGET_BASE) >> 2) + 1;
+        sm = aplic->sourcecfg[irq] & APLIC_SOURCECFG_SM_MASK;
+        if (sm == APLIC_SOURCECFG_SM_INACTIVE) {
+            return 0;
+        }
          return aplic->target[irq];
      } else if (!aplic->msimode && (APLIC_IDC_BASE <= addr) &&
              (addr < (APLIC_IDC_BASE + aplic->num_harts * APLIC_IDC_SIZE))) {