On Wed, Jul 16, 2025 at 11:53:50AM +0200, Luc Michel wrote:
> Refactor the ADMA creation using the VersalMap structure.
>
> Note that the connection to the CRL is removed for now and will be
> re-added by next commits.
>
> Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
> ---
> include/hw/arm/xlnx-versal.h | 2 -
> hw/arm/xlnx-versal-virt.c | 28 --------------
> hw/arm/xlnx-versal.c | 72 ++++++++++++++++++++++++------------
> 3 files changed, 48 insertions(+), 54 deletions(-)
>
> diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
> index 1fcc2b623da..4eeea98ff34 100644
> --- a/include/hw/arm/xlnx-versal.h
> +++ b/include/hw/arm/xlnx-versal.h
> @@ -15,11 +15,10 @@
>
> #include "hw/sysbus.h"
> #include "hw/cpu/cluster.h"
> #include "hw/or-irq.h"
> #include "hw/intc/arm_gicv3.h"
> -#include "hw/dma/xlnx-zdma.h"
> #include "hw/rtc/xlnx-zynqmp-rtc.h"
> #include "qom/object.h"
> #include "hw/usb/xlnx-usb-subsystem.h"
> #include "hw/misc/xlnx-versal-xramc.h"
> #include "hw/nvram/xlnx-bbram.h"
> @@ -75,11 +74,10 @@ struct Versal {
>
> struct {
> MemoryRegion mr_ocm;
>
> struct {
> - XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS];
> VersalUsb2 usb;
> } iou;
>
> /* Real-time Processing Unit. */
> struct {
> diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
> index 09f87dc76dd..1922a90019c 100644
> --- a/hw/arm/xlnx-versal-virt.c
> +++ b/hw/arm/xlnx-versal-virt.c
> @@ -202,37 +202,10 @@ static void fdt_add_usb_xhci_nodes(VersalVirt *s)
> qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.dwc);
> qemu_fdt_setprop_string(s->fdt, name, "maximum-speed", "high-speed");
> g_free(name);
> }
>
> -static void fdt_add_zdma_nodes(VersalVirt *s)
> -{
> - const char clocknames[] = "clk_main\0clk_apb";
> - const char compat[] = "xlnx,zynqmp-dma-1.0";
> - int i;
> -
> - for (i = XLNX_VERSAL_NR_ADMAS - 1; i >= 0; i--) {
> - uint64_t addr = MM_ADMA_CH0 + MM_ADMA_CH0_SIZE * i;
> - char *name = g_strdup_printf("/dma@%" PRIx64, addr);
> -
> - qemu_fdt_add_subnode(s->fdt, name);
> -
> - qemu_fdt_setprop_cell(s->fdt, name, "xlnx,bus-width", 64);
> - qemu_fdt_setprop_cells(s->fdt, name, "clocks",
> - s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
> - qemu_fdt_setprop(s->fdt, name, "clock-names",
> - clocknames, sizeof(clocknames));
> - qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
> - GIC_FDT_IRQ_TYPE_SPI, VERSAL_ADMA_IRQ_0 + i,
> - GIC_FDT_IRQ_FLAGS_LEVEL_HI);
> - qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
> - 2, addr, 2, 0x1000);
> - qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
> - g_free(name);
> - }
> -}
> -
> static void fdt_add_rtc_node(VersalVirt *s)
> {
> const char compat[] = "xlnx,zynqmp-rtc";
> const char interrupt_names[] = "alarm\0sec";
> char *name = g_strdup_printf("/rtc@%x", MM_PMC_RTC);
> @@ -556,11 +529,10 @@ static void versal_virt_init(MachineState *machine)
>
> fdt_create(s);
> versal_set_fdt(&s->soc, s->fdt);
> fdt_add_gic_nodes(s);
> fdt_add_timer_nodes(s);
> - fdt_add_zdma_nodes(s);
> fdt_add_usb_xhci_nodes(s);
> fdt_add_rtc_node(s);
> fdt_add_bbram_node(s);
> fdt_add_efuse_ctrl_node(s);
> fdt_add_efuse_cache_node(s);
> diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
> index 062f9a91a6c..97cd991be10 100644
> --- a/hw/arm/xlnx-versal.c
> +++ b/hw/arm/xlnx-versal.c
> @@ -28,10 +28,11 @@
> #include "hw/arm/fdt.h"
> #include "hw/char/pl011.h"
> #include "hw/net/xlnx-versal-canfd.h"
> #include "hw/sd/sdhci.h"
> #include "hw/net/cadence_gem.h"
> +#include "hw/dma/xlnx-zdma.h"
>
> #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
> #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f")
> #define GEM_REVISION 0x40070106
>
> @@ -58,10 +59,20 @@ typedef struct VersalMap {
> size_t num_prio_queue;
> const char *phy_mode;
> const uint32_t speed;
> } gem[3];
> size_t num_gem;
> +
> + struct VersalZDMAMap {
> + const char *name;
> + VersalSimplePeriphMap map;
> + size_t num_chan;
> + uint64_t chan_stride;
> + int irq_stride;
> + } zdma[2];
> + size_t num_zdma;
> +
> } VersalMap;
>
> static const VersalMap VERSAL_MAP = {
> .uart[0] = { 0xff000000, 18 },
> .uart[1] = { 0xff010000, 19 },
> @@ -76,10 +87,13 @@ static const VersalMap VERSAL_MAP = {
> .num_sdhci = 2,
>
> .gem[0] = { { 0xff0c0000, 56 }, 2, "rgmii-id", 1000 },
> .gem[1] = { { 0xff0d0000, 58 }, 2, "rgmii-id", 1000 },
> .num_gem = 2,
> +
> + .zdma[0] = { "adma", { 0xffa80000, 60 }, 8, 0x10000, 1 },
> + .num_zdma = 1,
> };
>
> static const VersalMap *VERSION_TO_MAP[] = {
> [VERSAL_VER_VERSAL] = &VERSAL_MAP,
> };
> @@ -484,34 +498,49 @@ static void versal_create_gem(Versal *s,
> }
> qemu_fdt_setprop(s->cfg.fdt, node, "interrupts", irq_prop,
> sizeof(uint32_t) * map->num_prio_queue * 3);
> }
>
> -
> -static void versal_create_admas(Versal *s, qemu_irq *pic)
> +static void versal_create_zdma(Versal *s,
> + const struct VersalZDMAMap *map)
> {
> - int i;
> + DeviceState *dev;
> + MemoryRegion *mr;
> + g_autofree char *name;
> + const char compatible[] = "xlnx,zynqmp-dma-1.0";
> + const char clocknames[] = "clk_main\0clk_apb";
> + size_t i;
>
> - for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) {
> - char *name = g_strdup_printf("adma%d", i);
> - DeviceState *dev;
> - MemoryRegion *mr;
> + name = g_strdup_printf("%s[*]", map->name);
>
> - object_initialize_child(OBJECT(s), name, &s->lpd.iou.adma[i],
> - TYPE_XLNX_ZDMA);
> - dev = DEVICE(&s->lpd.iou.adma[i]);
> + for (i = 0; i < map->num_chan; i++) {
> + uint64_t addr = map->map.addr + map->chan_stride * i;
> + int irq = map->map.irq + map->irq_stride * i;
> + g_autofree char *node;
> +
> + dev = qdev_new(TYPE_XLNX_ZDMA);
> + object_property_add_child(OBJECT(s), name, OBJECT(dev));
> object_property_set_int(OBJECT(dev), "bus-width", 128, &error_abort);
> object_property_set_link(OBJECT(dev), "dma",
> OBJECT(get_system_memory()), &error_fatal);
> - sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
> + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
>
> mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
> - memory_region_add_subregion(&s->mr_ps,
> - MM_ADMA_CH0 + i * MM_ADMA_CH0_SIZE, mr);
> + memory_region_add_subregion(&s->mr_ps, addr, mr);
>
> - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_ADMA_IRQ_0 +
> i]);
> - g_free(name);
> + versal_sysbus_connect_irq(s, SYS_BUS_DEVICE(dev), 0, irq);
> +
> + node = versal_fdt_add_simple_subnode(s, "/dma", addr, 0x1000,
> + compatible, sizeof(compatible));
> + qemu_fdt_setprop_cell(s->cfg.fdt, node, "xlnx,bus-width", 64);
> + qemu_fdt_setprop_cells(s->cfg.fdt, node, "clocks",
> + s->phandle.clk_25mhz, s->phandle.clk_25mhz);
> + qemu_fdt_setprop(s->cfg.fdt, node, "clock-names",
> + clocknames, sizeof(clocknames));
> + qemu_fdt_setprop_cells(s->cfg.fdt, node, "interrupts",
> + GIC_FDT_IRQ_TYPE_SPI, irq,
> + GIC_FDT_IRQ_FLAGS_LEVEL_HI);
> }
> }
>
> #define SDHCI_CAPABILITIES 0x280737ec6481 /* Same as on ZynqMP. */
> static void versal_create_sdhci(Versal *s,
> @@ -970,18 +999,10 @@ static void versal_create_crl(Versal *s, qemu_irq *pic)
> object_property_set_link(OBJECT(&s->lpd.crl),
> name, OBJECT(&s->lpd.rpu.cpu[i]),
> &error_abort);
> }
>
> - for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) {
> - g_autofree gchar *name = g_strdup_printf("adma[%d]", i);
> -
> - object_property_set_link(OBJECT(&s->lpd.crl),
> - name, OBJECT(&s->lpd.iou.adma[i]),
> - &error_abort);
> - }
> -
> object_property_set_link(OBJECT(&s->lpd.crl),
> "usb", OBJECT(&s->lpd.iou.usb),
> &error_abort);
>
> sysbus_realize(sbd, &error_fatal);
> @@ -1161,12 +1182,15 @@ static void versal_realize(DeviceState *dev, Error
> **errp)
>
> for (i = 0; i < map->num_gem; i++) {
> versal_create_gem(s, &map->gem[i]);
> }
>
> + for (i = 0; i < map->num_zdma; i++) {
> + versal_create_zdma(s, &map->zdma[i]);
> + }
> +
> versal_create_usbs(s, pic);
> - versal_create_admas(s, pic);
> versal_create_pmc_apb_irq_orgate(s, pic);
> versal_create_rtc(s, pic);
> versal_create_trng(s, pic);
> versal_create_xrams(s, pic);
> versal_create_bbram(s, pic);
> --
> 2.50.0
>
