On Tue, 29 Jul 2025 at 17:17, Zenghui Yu <zenghui...@linux.dev> wrote: > > As per the arm-vgic-v3 kernel doc [1]: > > Accesses to GICD_ICPENDR register region and GICR_ICPENDR0 registers > have RAZ/WI semantics, meaning that reads always return 0 and writes > are always ignored. > > Remove the useless writes to ICPENDR registers in kvm_arm_gicv3_put(). > > [1] https://docs.kernel.org/virt/kvm/devices/arm-vgic-v3.html
The kernel doesn't implement any state behind these registers today, but that doesn't inherently mean it will never do so or that it never did do so. Since we have the state fields in the GICv3State struct (for the benefit of TCG) and the kernel defines the accessors for it, I prefer to leave this code in QEMU, and leave it up to the kernel whether it provides any state behind them. thanks -- PMM
